Research On High-speed Serial Link Based Memory Interface Design And Its Application

In recent years,with the continuous growth of information transmission requirements,high-speed serial link technology has been developed rapidly and widely used.The advantages include high data rate and signal quality,and small number of transmission channels and input output pins.High-speed serial link is gradually becoming an important method for data transmission between modern computer systems and chips.However,in the current design of memory,the parallel interface is still widely used,and the access bandwidth of the memory is improved by a wider data interface and a higher clock frequency.This design approach directly leads to high IO pins overhead and power consumption,as well as severe signal integrity issues due to increased layout difficulty.Although the latest 3D memory devices have been proposed for serial transmission,their high cost has limited the application to a few high performance computing chips.In this thesis,the traditional memory with parallel interface design requires a large number of input and output pins.A memory interface design based on high-speed serial link is proposed to replace the traditional parallel interface,which reduces the number of pins of memory interface greatly,making the expansion of memory capacity become possible,this effectively supports the current storage requirements for big data application.Based on the design,this thesis further proposes a memory interface application based on high-speed serial transmission.With the feature that the serial transmission can be used to reduce the overhead during transmission,this thesis proposed a simple and effective image data incremental encoding and decoding design for deep learning application.This encoding and decoding design is combined with high speed serial transmission memory interface,which reduces the redundant image information and improves the effective bandwidth and efficiency of the transmission.The design proposed in this thesis is based on the traditional two-dimensional memory structure,with low design and implementation overhead,which provides a useful reference for the design of high-speed serial memory interface in the future.Based on the Xilinx FPGA platform,this thesis completes a prototype implementation of a high-speed serial transmission for memory interface with the high-speed serial transiceiver,and integrates the proposed image data incremental encode and decode module.The experimental result shows that the memory interface design using high-speed serial link can reduce the number of pins to 25% of the number in parallel transmission interfaces,and the power consumption can be saved by 18%.Furthermore,the image data incremental encoding and decoding result shows that average of 33% of data compression can be achieved,and run length coding and decoding result shows that 78% of data compression can be achieved at the cost of small increase in delay and power consumption.Thereby this method effectively increases the bandwidth of the transmitted data.