| Parallel bus is a commonly used data transmission bus.At present,the speed of parallel bus single channel is up to the order of gigabit per second,so the signal integrity problems such as reflection and crosstalk can not be ignored.DDR SDRAM is a kind of dynamic random access memory based on parallel bus.In practical application,its ultra-high interface rate exposes serious signal integrity problems.There are two ways to evaluate the signal performance of high-speed interface: eye graph test and jitter tolerance test.These two testing methods need to rely on digital communication analyzer,bit error meter and other general instruments to build a complex testing platform,which is undoubtedly time-consuming and expensive.In order to meet the testing requirements of signal integrity of DDR interface,a high-speed parallel bus interface test system based on FPGA is designed to evaluate the performance of DDR interface physical layer.The main research contents of the topic are as follows:1.Hardware scheme and circuit design.According to the requirements of the test index,the hardware scheme which can carry the functional verification of the subject is designed.It includes low jitter clock circuit,pin drive / measurement circuit and system communication scheme.Among them,the pin drive / measurement circuit is realized by the cooperation of Pin Electronics(PE)chip and ADC analog-to-digital converter chip.2.Bit Error Rate(BER)eye diagram scanning and parameter estimation.Eye diagram analysis is one of the important methods to evaluate the quality of high-speed signals in PHY layer.In this thesis,based on the principle of BER eye diagram,the error statistics of each offset sampling point in the time and amplitude plane are realized by the CDR unit of the FPGA high-speed transceiver.The complete BER eye diagram is obtained by coloring the BER contour lines in the plane.The error rate data of each sampling point in the eye diagram are analyzed to achieve the estimation of eye height,eye width,and other parameters.3.Design of test vector synthesis and transceiver function.FPGA high-speed transceiver serialization and de-serialization function enables it to support ultra-high speed data transceiver.This thesis proposes a vector synthesis method based on code pattern broadening,which adjusts the edge position and output rate of serialized data by operating the parallel data bit width in the process of parallel-serial conversion.On this basis,the test vector synthesis with edge adjustment resolution of 40 ps is realized.4.Research and implementation of jitter injection method.The jitter tolerance test of DDR interface requires the test system to synthesize the code pattern vector with controllable jitter.This thesis analyzes the transmission process of jitter from reference clock to high-speed data,studies the injection method of clock jitter,and puts forward two edge jitter injection schemes: fine phase shift method and tap delay method.Finally,the functions and indexes of the system are tested and verified.the results show that the 128 channel DDR interface test system designed in this thesis supports BER eye image scanning,edge jitter injection and pin electrical parameter measurement,and each index meets the testing requirements of high-speed parallel interface. |
