Design And Implementation Of The External Memory Interface In Video-DSP

The technology for audio/video coding/decoding is mainly implemented by two methods, the specific coder/decoder chips, and the coding/decoding algorithms based on DSPs. The latter becomes the mainstream for video coding/decoding due to its strong flexibility, extendibility and controllability. High data stream and bandwidth requirement is the main characteristic of video processing. Thus, the performance of memory interface is vital to VDSP. The high-performance DSP processor YHFT-Dx designed by our university has strong processing ability, but the low speed of memory access limits its utilization for audio/video coding/decoding.To improve the speed of memory access of DSPs, an innovative external memory interface for YHFT-Dx is proposed in this thesis, which enhances the interface access ability. The key technologies of this design include the asynchronous FIFOs based on buffers, the fixed request priority based on circling token, first reading based on the cache offset, and memory controlling of double channels and multi-frequency. Furthermore, this thesis gives the detail design of read/write requests dispatching unit, the buffer unit of read/write requests, the memory control unit of DDR2 SDRAM, the memory control unit of asynchronous memories, unit of controlling registers and some other components, and gives the detail function verification for this module. The external memory interface designed for YHFT-Dx can support not only asynchronous memories but also DDR2 SDRAM which have higher operation frequency and larger capacity.The implementation of memory interface supporting DDR2 SDRAM memories further improves the performance of VDSP, expands its application range, and lays a good foundation for further study.