Design And Optimization Of SDRAM Memory Interface In High-Definition Video Decoder

With the development of digital audio and video industry and the progress of audio and video codec technology, the hardware design of video decoder becomes more complex. The decoding system need to exchange a lot of temporary datas with the memory. Because of the character of SDRAM and the huge quantity of datas, the SDRAM bandwidth must be reduced for the high-definition real-time decoding, so a viable and efficient SDRAM interface needs to be designed.According to the character of AVS and H.264 high-definition video decoder and the quality of SDRAM, This thesis makes an analysis for the memory requirement and optimization in high-definition video decoding system, and describes the design of video decoder chip with the "life-view" chip series of Chinese Academy of Science. A multi-bank operation memory interface for SDR SDRAM and DDR SDRAM is designed, using several methods such as remapping of picture addresses in memory, optimization of request order from each module and the order of reading and writing, efficient multi-pipeline organization with the way of state prediction, and the reduction of idle state cycles.It has been approved that the data communication rate of the memory interface discussed in this thesis can reach more than 80%, and fully meets the requirement of AVS and H.264 high-definition video decoding. This design can also be used in other environment which requires high efficiency of memory interface.