Design And Testing Of Multi-standards FPGA I/O Circuit

With the rapid development of semiconductor technology and communication technology, requirements of high speed data transmission are increasing. Therefore, FPGA, as the most important key device in communication product fields nowadays, must meet this demand. The design and manufacture of FPGA I/O is essential for improving product performance because I/O interface circuit is the only bridge between FPGA and the outside. Many communication protocols have been proposed to achieve the high speed data transmission, FPGA I/O needs to improve its transmission speed compatible with these protocols. I/O interface circuits of many commercial FPGA products of Xilinx, Altera corporations have been compatible with the international general communication protocol standards including LVCMOSn LVTTL、PCL、GTL、 GTLP、SSTL、HSTL、LVDS、LDT、LVPECL、BLVDS、ULVDS with their speed up to Gbps.Under such background, multi-standards FPGA I/O is studied in this thesis. After introducing the background and significance of FPGA, general I/O and FPGA I/O are analyzed separately. On this basis, three main design issues during the design are presented:1) compatible with multiple communication standards including LVDS;2) guarantee the signal integrity in the high speed communication; 3) the speed of 1 Gbps LVDS transceiver. Combined with other references, reasonable and effective solutions according to the specific problems are worked out:1) design the transceiver circuits of single-ended standards, pseudo-differential-ended standards and differential-ended standards separately after functional partitioning and reuse the circuits as much as possible; 2) using the advanced DCI technology; 3) using pre-emphasis technology in the LVDS transmitter.Then, the layout design and chip test solution are descriped. A shift register circuit is employed to implement the configurable function.This FPGA I/O circuit was taped out using SMIC 1P10M 65nm CMOS technology. At last, the chip test result is given and it shows that the chip performance meets the specification well. As a part of a 863 project, this study is a valuable exploration for high performance FPGA I/O circuits.