The Design And Realization Of LVDS Ring Bus In The Universal Test Bench Based On FPGA

The automatic testing of the missile telemetry system has upgrading needs of universality and modularization. In this thesis, based on research background of the universal demands of the specialized automated testing bench of telemetry system, the development status of testing system buses at home and abroad is studied. The LVDS ring bus based on FPGA is studied to achieve high-speed transmission of the multi-load system.Combined the advantages of high-speed transmission of LVDS bus with those of high efficiency, fair access of the ring bus in the multi-load system, the LVDS ring bus based on FPGA is designed, especially, the design of physical layer, data link layer and application layer of the bus protocol is introduced in detail.The bus used in the multi-load system has advantages of high-speed transmission, high dependability and high real-time. Currently, the bus has been applied in some telemetry universal test benches. The hardware structure and the completive functions of the bus protocol in the universal test bench are introduced in this thesis. FPGA is used as the main logic controller and the control logic of the LVDS ring bus protocol is implemented in FPGA.Several key technologies in the implementation of bus system are designed and studied, including LVDS high-speed design and layout skills, high-speed data caching technology and multi-data sources processing technology and so on. The impedance matching design of the LVDS transmission, PCB design requirements, the matching design of the high-speed transmission interface and the design of multi-data sources processing of the application layer according to the requirement of uploading test data of the test bench are mainly introduced.Currently, the bus system is used in some test bench projects such as the memory test system, which fully shows the universality and scalability.