The Design Of LVDS Interface System

In recent days, with the development of information technology, microprocessor, multimedia, virtual reality and network require higher data transferring speed and wider data bandwidth; further more, the reduction of the power consumption has been greatly concerned in portable systems. Whereas, current point to point physical layer interfaces, such as RS-422, RS-485 and SCSI are not competent for this difficult task, because of the limitations in speed, noise, EMI, power consumption and cost. Therefore, a novel and effective solution is needed to overcome the bottleneck of I/O interface and realize high-speed data transmission, low noise and low cost. Low Voltage Differential Signaling (LVDS) is a new technology developed to meet this demand. LVDS achieves a greatly high speed and significant power reduction by means of low swing; LVDS achieves low noise and low EMI by means of differential scheme for transmission.LVDS interface circuit has been an important topic in the field of analog and digital integrated circuit design because of these attractive merits.This paper is based on HJTC 0.35μm CMOS mixed digital-analog technology and the main study includes the LVDS system architecture, circuit design and system simulation. System architecture mainly concentrates on LVDS standards, technical parameters, basic principle and transmitter architecture. According to the system architecture, the paper focuses on the design of band-gap, PLL, 8-bit serializer, transmitter and receiver.In the end, the entire LVDS interface system and MOS parameters are optimized and simulated. The simulation results show that the optimized transceiver is fully compatible with the LVDS standard and a simulated waveform at 1.0Gbps is given.