The Design Of LVDS Interface Transceiver With High Speed And Low Power

By the development of electronic information technology,the amount of data that be transmitted is increasing,and the application of high-speed signal transmission is increasing day by day.People put forward higher requirements for information transmission rate.Traditional I/O interfaces cannot meet this requirement due to defects in speed,noise,power consumption,etc.Low Voltage Differential Signaling(LVDS: Low Voltage Differential Signaling)technology is characterized by its high speed,low voltage,low power consumption and noise immunity.It plays an important role in high-speed data transmission systems.Based on the research on LVDS transceiver system,the design of high-speed LVDS interface circuit with data rate of 12.5Gbps is realized.In the receiver part,a cascaded receiver with current-reuse pre-amplifier is designed,which effectively improves the energy efficiency.The whole system adopts low-voltage 0.9V power supply and includes four blocks:transmitter,receiver,bandgap reference and frequency divider circuit.In the transmitter,the single-ended TTL signal is converted into a double-ended differential signal through a single-ended to differential circuit,and then the driver generates an LVDS signal with a common-mode voltage of 450 m V and a swing of 300 m V,and the common-mode feedback is used in the driver to stabilize the common mode level;in the receiver,a cascaded receiver is designed,the energy efficiency of the receiver is improved by the current-reuse pre-amplifier,and the receiver with high speed and low power consumption is realized,and the receiver can recover the input signal with an amplitude of 50 m V and a maximum bandwidth of 12.5GHz;the bias voltage and reference level required by the system are provided by the bandgap reference source.Since the whole system uses a low-voltage power supply of 0.9V,this paper designs a ratiometric output current-mode bandgap reference based on sub-threshold MOS that capable of operating under 0.9V,providing a reference level and bias voltage.In order to output the high-frequency square wave signal for the off-chip observation,this design implements a frequency divider circuit composed of a D flip-flop based on a transmission gate and an inverter and a D flip-flop based on a CML(Current mode logic),respectively.The project is designed with cadence,simulated and verified with spectre,and a full-custom layout design of the overall system is carried out.The design uses TSMC 28 nm CMOS 1P10 M process,and the DRC(Design rule check)and LVS(layout versus schematic)of the layout are carried out through calibre.Each block has been verified by pre-and post-simulation.According to the post-simulation results,a transmitter capable of generating12.5Gbps LVDS signals is implemented;a receiver with a maximum bandwidth of 12.5GHz and an energy efficiency of 0.064 p J/bit is realized;A bandgap reference source with a temperature coefficient of 14.84ppm/℃ in the temperature range of 0℃ to 85℃;for the situation that high-frequency square wave signals are difficult to transmit from on-chip to off-chip,frequency dividers with two structures are implemented,and The frequency division function is verified by post-simulation.After the system simulation verification,the design of the reliability before tape-out was carried out.The IO ring used TSMC general IO cells,and the latch-up effect,antenna effect,ESD protection,etc.were studied and related designs were carried out on the chip.The pre-simulation verification of the overall system on the chip was carried out and finally tape-out.Then a test plan was drawn up and a test PCB was designed.