The Design And Implementation Of LVDS Conversion Board Based On FPGA

High-speed video transmission is widely used in the fields of HDVD,mobile communication terminal and military flight displays at present.In a number of specific occasions such as motion capture,object tracking,image processing can not meet the requirements of low-latency and high-speed.There is a solution to the problem of different interface adapting and the demand of real-time image processing.In this thesis,an universal video-processing system is built by way of coordinating the debugging of hardware and software and algorithm designing.At the beginning,the VGA analog signal is converted to digital signal by encoding module in the system.Then,some algorithms are implemented in the core board such as filtering,grayscale processing and edge detecting.Last,the signal is output in LVDS signal.Finally,the VGA signal at a resolution of 1920 * 1080 at 60 Hz is converted to LVDS differential signal.This platform is based on FPGA parallel processing architecture,compared with CPU GPU architecture,it has the advantages of high-performance,low-latency and low-power consumption.In this thesis,some creative achievements include algorithm reconstructing in Verilog HDL,data catching by DDR2 SDRAM,algorithm application combined with OCR.The keystone of this research is indicated as follows:1?demand assessment.The scheme of Altera Cyclone IV + STM32 + peripheral devices is established.The relevant datasheets are studied.2?the platform is built by refering to technical manual,designing DXP system schematic and PCB layout.The technique of separation design is normally used in the design,including a module of interface conversion and a module of algorithm processor.3?the logic program of key components are designed,including time sequence logical control,serial communications,external cache based on DDR2.The time sequence logical control follows VESA standard.The serial communications includes epistasis software and embedded software.The DDR2 design adopts the way of IP core to test read-write.4?the demand of real-time image-processing operation is solved.Mean filter,median filter and edge extraction are reconstructed by Verilog HDL and simulation test is correct.5? each module is debugged,including power-supply system,interface conversion and algorithm implementation.The implementation of the FPGA and Matlab in algorithm are compared in terms of performance and the delay is within 20 ms.The processed image is applicated in technology of OCR.Final results indicate that the system designed in this thesis achieves the targets: interface converting,video processing and displaying stably.