Research And Design Of High - Speed Configurable FPGA I / O

FPGA has always been an important part of the IC industry since the first FPGA was born in1985. With the development of IC technology as Moore’s Law, the circuit density, power comsumption and energy efficiency of FPGA also get close to those of the ASIC. In addition, the product of FPGA can better fit the consumer electronics market, which changes fast as FPGA can be turned into powerful functional IC. What’s more, FPGA are also widely used in the communication equipments. Many FPGA companies introduce lots of FPGA products for communication equipments, which have a variety of communication IP. And also lots of communication equipment manufacturers adopt FPGA for their products instead of ASIC or ASSP. As the bridge of the FPGA core and the outside world, FPGA I/O also comes to the speed of Gbps.Firstly the significance of FPGA I/O research is reviewed. And then basic structure of FIGA and I/O are discussed. Also DC character and terminal structure of each FPGA standards are carefully explained as well as the effect of the transmission line to the signal. The mainly purpose of this work is the research and realization of the FPGA I/O, which, according to the multiple standards, is particificated into these parts:the Receiver, the Driver, LVDS circuits, DCI (Digital controlled impedance). Then focused on the circuits realization of each standards, the receiver is mainly composed of Schmitt trigger and Hysteresis comparator, which are anti-noise; the driver part is mainly composed of a slew-rate control part and output buffer-array, which is designed according the demand of current driving capability and DCI; LVDS driver is realized using the pre-emphasis technique to compensate the effect of the transmission line in high frequency, and LVDS receiver adopted the Rail-to-Rail structure to meet the demand of0.3V-2.2v input common mode voltage; the last is the realization of DCI part, including the structure and algorithm.This chip is implemented in SMIC1P10M65nm CMOS process with multiple-level powers according to the standards, the core area is1.5mm*0.8mm. This chip can totally meet the demand of the spec and fulfill the variety of standards.