Research And Design Of S/H In High-Speed High-Resolution ADC

High speed high resolution analog to digital converter (ADC) has attracted much attention in ADC design currently, and it generally can be implemented in pipelined structure. Sample and hold circuit (S/H) is a critical module in pipelined ADC, which is located at the beginning of the signal processing chain. Its speed and resolution restrict the maximum conversion rate and maximum resolution of the ADC. This thesis research and design an S/H in a 14-b 100MSPS pipelined ADC based on TSMC 0.18μm CMOS mixed signal standard process.In this thesis, design technology of S/H in pipelined ADC is researched and analyzed. Firstly, basic mechanics of pipelined ADC, basic mathematical theory of S/H and its specification are introduced. Then, structures of S/H and its sub-circuits are analyzed in detail, which include bootstrapped switch, fully differential op amp and common mode feedback circuit. At the same time, the impact of several non-ideal factors on the performance of S/H is presented, such as nonlinearity of the switch resistance, charge injection effect, clock feed-through effect, incompletely settling of op amp. Also, design methods are proposed to reduce the non-ideality and improve the performance of sample and hold circuit.At the end, main parameters of the sub-circuits of 14-b 100MSPS pipelined ADC are calculated utilizing mathematical model. Based on this calculation, a flip-around S/H is designed, and it was verified with simulation in Cadence. With a 2Vpp 10.058 MHz sinusoidal input signal, the simulation result of the 1024 points Fast Fourier Transform (FFT) of the output voltage shows that the spurious free dynamic range (SFDR) is 103.5dB, which satisfies the requirement of 14-b pipelined ADC. This S/H can be applied in the 14-b 100MSPS pipelined ADC.