Research On Encoder And Decoder Of Turbo Codes And Its Implementation With FPGA

The aim of this paper is to implement the encoder and the decoder of Turbo codes with FPGA. The theory of encoding and decoding of Turbo codes and the iterative decoding algorithms are studied, as well as how to implement them with hardware language has been discussed in the paper.Firstly, the paper discusses the theory of encoding and decoding of Turbo codes and introduces three encoding structures, such as PCCC, SCCC and HCCC, while discussing the critical factors of the encoding of Turbo codes. Secondly, the paper introduces the decoding structure of Turbo codes and investigates two families of decoding algorithms: MAP algorithm and SOVA algorithm. The comparison of MAP algorithm and SOVA algorithm is also discussed.Based on the study of the theory of Turbo codes and the trade-off between the performance and the degree of implementation difficulties, the paper adapts PCCC encoding structure and SOVA decoding algorithm. In terms of software development, a Turbo encoder and a Turbo decoder have been implemented in VHDL. In addition, an AWGN digital discrete channel has also been implemented for the purpose as test bench for the Turbo codes system. According to the consideration of performance, cost and future improvement needs, Altera Cyclone II device has been chosen as the hardware design scheme for the Turbo codes system and the circuits of each block has been designed, as well as the PCB design of the system.