Research On Encoder And Decoder For Turbo Codes With FPGA

The aim of this paper is to implement the decoder of turbo codes with FPGA. The iterative decoding algorithms and how to implement them with hardware language have been discussed in the paper.Firstly, the paper introduces the theory of encoding and decoding of turbo codes, and the simulation analysis on the decoding performance of MAP,MAP_LOG,MAX_LOG_MAP algorithms with the C language in computer have been given. Secondly, according to a great deal of simulation results, the paper investigates the key design parameters which could greatly influence the performance of MAP algorithm.Finally,We choose MAX_LOG_MAP algorithm as the scheme of hardware implemention considering the simplicity of hardware implementation.This paper is designed with modularization, and has proposed some improved schemes on the basis of the thing that has been designed to each module, improved the synchronous question of the turbo encoder, and has studied the hardware implementation of turbo sub-block parallel decoding algorithm.In the design, the"top-down"and"from bottom to top "methods have been used synthetically. Then turbo encoder and decoder have better flexibility by dividing up the function modules, setting up the systematic parameters reasonably, and transferring the parameters between the modules.