Research And Implementation Of RS-Turbo Concatenated Encoder And Decoder

In recent years,with the rise of intelligent driving,remote surgery,intelligent agriculture and other fields,the effectiveness and reliability of information in communication systems are becoming more and more important.Channel coding technology is one of the important technologies to ensure the reliability of communication.However,with the increasing requirements for data transmission speed and reliability today,it is difficult to meet the needs of some communication systems to correct continuous burst errors using a single code under the same resource allocation.Based on this,this paper proposes the implementation scheme of the cascade encoder-decoder with RS code as the outer code and Turbo code as the inner code.The main work of this paper is as follows:(1)In order to solve the problem that the concatenated outer code needs a BCH code that can correct the continuous errors caused by the decoding of the inner code,this paper proposes an implementation method of RS(31,15)encoder-decoder on FPGA.In the implementation of RS decoder,the hardware implementation flow of the Berlekamp-Massey decoding algorithm is given.In the adjoint polynomial calculation module,a fully parallel implementation is adopted,which reduces the computing time by increasing the use of resources.In the key equation solving module,the corresponding operations in the BM algorithm are simplified by using a look-up table,so that the operations such as multiplication and inversion of elements in the finite field are easy to implement in hardware.The bit error performance of the RS(31,15)decoder is simulated,and the resource occupation and throughput of the RS(31,15)decoder on the ZCU104 development board are given to illustrate the feasibility of the RS(31,15)decoder.(2)The concatenated inner code needs a binary code with strong error correction ability.This paper proposes a Turbo code with(2,1,3)convolutional codes as component codes and component code parallel structure as inner codes.The interleaver and deinterleaver of Turbo code are based on the 3GPP standard interleaver,and the SOVA algorithm is used for decoding.The hardware implementation of each module in Turbo codec is given,and the functional simulation of each module is verified.The error performance of the Turbo decoding algorithm is simulated under different decoding iterations in AWGN channel.Based on the SOVA decoding algorithm,the resource occupancy and throughput on the development board are given to illustrate the feasibility of the algorithm.(3)The implementation method of the RS-Turbo cascade code is given,and the ability of correcting the continuous burst error of the block interlever used in the RS-Turbo cascade code is analyzed and verified.The BER performance simulation of the RS-Turbo cascade codes implemented on ZCU104 development platform under different interleaver is given.Experiments show that the RS-Turbo codes meets the application scenarios of separate RS codes and Turbo codes in terms of hardware resource occupancy,system energy consumption and throughput,and can effectively improve the error plane problem of Turbo code.The coding gain of the RS-Turbo code is more than 3dB higher than that of RS code.The coding gain of concatenated codes is 1-1.5dB higher than that of Turbo codes.