The Sensitivity Analysis Of Power Supply Noise Of Digital PLL

Power supply noise is the most important source for timing jitter. A stable method called PDN has been put forward in order to reduce power supply noise utmostly in the power integrity engineering field. However, the power supply noise cannot be ignored in the design of PDN, because the package in the high speed interface shows a greater inductive. It causes timing jitter in system directly. Under its influence, different components in the circuit performance differently in jitter sensitivity or response. Thus, in the design and optimization of high speed I/O interface, it has a wider significance to describe the curve of the power sensitivity in the chip and conduct the design of the power distribution network.By putting up the HSPICE model of digital PLL we add different frequency noise in PLL’s power plane, and verify the bandpass filter characteristic of PLL by analysing the jitter of output signal. At the same time, according to the experimental data, this paper describes the intermodulation existence of different frequency noise in power planes. The measurement method of sensitivity curve is given in this paper, and the curve of PLL is drawn. Meanwhile the jitter sensitivity is proofed. The design ideas that the special power integrity pursuits purely low noise is broken. It is great guiding significance to put up the PLL model and draw the curve of sensitivity for the design of high speed serial interface.Developed two tool softwares, sensitivity analysis software and intermodulation software, are implemented with the method aboved. Additionally, the outputs of these two softwares are compared with the results of Custom Explorer. The results are proved to be the validity in this paper.