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Research Of Zero-crossing Based Pipelined ADC

Posted on:2017-02-18Degree:MasterType:Thesis
Country:ChinaCandidate:H LiuFull Text:PDF
GTID:2308330485984746Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Today digitization is a highly mentioned topic. The advanced process increases the integration of digital system and the speed of data progressing. Significant advantages of performance make many analog signal processing replaced by digital technology.However, the nature signals, such as sound, light, temperature and pressure, are all changing in analog way. As a pretext of analog and digital domain, the position of AD converter is still irreplaceable, but by the requirement of system it needs to speed up sharply. Meanwhile, with the popularity of portable device and intelligent device, the industry attaches much more great importance to low power design system. Against this background, structures with high speed and low power consumption have been put forward by universities and companies at home and abroad. One of the structures,ZCBC Pipelined ADC, not only preserves the high speed and high precision advantages of system architecture of Pipelined ADC, it also uses low power ZD in single stage circuit and replaces high power operational amplifier with a controlled current source,which reduces the system consumption greatly. Furthermore, the lack of feedback loop has solved the problems of system stability, and the simplified design has reduced the effects of process changes on system.In this paper a 10 bit, 50 MSps ZCBC pipelined ADC was proposed under 55 nm process.The system contains ten stages: one sample/hold circuit, eight 1.5 bit sub ADCs and one Flash ADC. Full-differential structure was used to increase the dynamic range and linearity. The ZCBC was made up of the OTA, delay cell and improved cascode current mirror. Comparators in the Flash ADC were replaced with ZCBCs so that Flash ADC could finish encoding in the sample phase and increase the settling time of MDAC.Digital foreground and background calibration ware used to calibrate the offset error.With 50 MSps fs and 16.89 MHz fin, the simulation result is SNDR 59 d B, SFDR67 d B, ENOB 9.5 bit. The power consumption from a 2.5 V supply is 27.5 mW.
Keywords/Search Tags:ADC, zero-crossing detect technology, zero-crossing detector, offset error calibration
PDF Full Text Request
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