Research On The Upset Mechanism Of CMOS Inverters Induced By The High Power Microwave

Nowadays, the electromagnetic environment surrounding modern electronic equipment has become increasingly complicated. In addition, for the microelectronics technology constantly updating and the size of semiconductor devices continuous decreasing, semiconductor devices in electronic equipment become more sensitive to high power microwave. What’s more, as the basic unit in digital circuits, CMOS inverter has been widely used for its low power consumption, large noise margin and high integration density as well as the advantages of low cost and easily design of CMOS technology, so that it is one of the typical devices which are vulnerable to high power microwave effect. Therefore, it is necessary to do some research on the upset effect of CMOS inverters induced by high power microwave.In this thesis, we establish a two-dimensional CMOS inverter model of the typical silicon-based structure by ISE-TCAD software based on 0.5 μm CMOS technology. And the HPM is assumed as a sinusoidal wave, and is injected into the source contact of the n-MOSFET to simulate the upset process that the HPM radiation energy couples into CMOS inverter through the back-door path. By analyzing the distribution of current density and temperature in the inverter, the upset effect is studied from the view of physics of semiconductor devices. The main work of the thesis are discussing the influence of parameters of microwave and different operation states on the upset effect in the CMOS inverter, and studying the thermal effect in upset process as well. The main conclusive results are listed as follows:1. By researching on the influence of the sinusoidal signal with different voltage amplitudes on the CMOS inverter, the conclusion is obtained that the higher voltage amplitude, the more easily upset effect occurs in the CMOS inverter. It is because that the latch mechanism is more easily triggered for high voltage amplitude.2. By studying the influence of the sinusoidal signal with different frequency on CMOS inverter, the result shows that CMOS inverter is more sensitive to the HPM disturb under the lower frequency condition. For a long negative half period of a pulse with a low frequency, the current path from the p-substrate contact to the n+ source contact forms and maintains a long time. Therefore, it will accumulate a lot of heat to triggerlatch-up and forms a low resistance path between the power and the ground under this situation in the inverter.3. By analyzing the thermal effect in the process of upset, we study the transfer phenomenon of the hot spot in CMOS inverter and find that the position of the hot spot will transfer from the cylinder of the p+ region of substrate to the channel region of p-MOSFET. If the HPM power is high enough, the 1st hot spot may cause burnout directly. If not, damage may also occur indirectly due to the 2nd hot spot.4. By studying the influence of different operation conditions on CMOS inverter, the conclusion is gained that the inverter is vulnerable to HPM under high level operation state. Due to the different operation states of the n-MOSFET and the p-MOSFET, the n-channel and the p-channel have different influences on the formation of the current path in upset process.