Single Event Effect Study And Hardened Design Of 65nm Bulk CMOS Process Latch Circuit

The achievements of human exploration in space were inseparable from the technology of integrated circuit.The systems in spacecraft such as satellites,spacecraft,and interstellar probes are all implemented by integrated circuits.Therefore,the increasing complexity of the radiation environment facing space vehicles in the universe,and the requirement for the reliability of integrated circuit is increasing.Meanwhile,the density of transistors on the chip increases in pace with device technology,and the Single Event Effect is the main reason of aviation system failure.As an important part of the integrated circuit,the latch cell can effectively reduce the probability of soft errors in the integrated circuit.In this paper,65 nm CMOS technology is the basis,the reinforcement of inverters is studied,and the source isolation technology and body bias effect are simulated and analyzed based on PMOS transistor.Then the NMOS transistor is hardened and simulated,and a latch cell hardened structure is proposed combined with polarity hardened technology.The main contents are as follows:(1)The complex space radiation environment faced by aircraft and the radiation effect are introduced.Then,the group of Single Event Effects and the principle of charge generation and collection under CMOS circuits are introduced.Finally,the methods of anti-radiation hardening of CMOS circuits are introduced from different aspects.(2)Study on the reinforcement of inverter.Illustrated by the example of PMOS transistor in the inverter,a simulation analysis of source isolation technology shows that source isolation technology can effectively reduce SET pulse intensity.The charge sharing effect of bombarded transistors with its adjacent transistors will be weakened with increasing of the layout spacing,by analyzing of the hole current density in the n-well found that increasing the layout spacing can reduce the number of holes collected by adjacent transistors,that is,reducing the impact of the bombarding transistor on adjacent transistors.The simulation analysis of body bias effect shows that the intensity of SET pulse decreases with the decrease of body bias voltage.The hardened simulation of NMOS transistor shows that the proposed hardened circuit can reduce the width of SET pulse.(3)A latch cell is proposed by using polarity hardening technology.The latch cell uses a fast data channel between the input terminal and the output terminal,which reduces the data transmission delay.There are six storage nodes inside the cell,all of which are surrounded and hardened by all NMOS transistors or all PMOS transistors,reducing the number of sensitive nodes and improves the anti-radiation performance of the latch cell combined with layout optimization.The latch cell is injected with error pulse to simulate the particle bombardment source,the results indicated that the cell has better performance against multi-node flipping.