Research Effects Of CMOS NAND Gate Induced By High Power Microwave

In the information age,the science and technology is developing at rapid speed.With the increasing use of the wireless communication system and the feature size being smaller due to the development of semiconductor technology,the electronic system is exposed in an increasingly complex electromagnetic environment,which poses a great threat.High power microwave(HPM),a typical source of electromagnetic environment,is a kind of electromagnetic wave with high power and high frequency,which can be easily coupled into the electronic system.The short time,large scope,strong destructiveness and rapid development can hardly be ignored by the modern scientific research personnel.As for the semiconductor devices and integrated circuits,due to the development of technology,with size getting smaller,frequency getting higher and power consumption getting lower due to technology development,electronic system has become increasingly sensitive to the electromagnetic environment which is under rapid development.Therefore,it is more important to do research on the protection of high power microwave technology and electronic system for HPM.But the basic characteristics of the device and effects and mechanism of HPM must be considered in the first place.As a basic logic unit of modern digital integrated system,the CMOS NAND gate and its universal application becomes the focus of this thesis.A series of studies on the upset effect and failure effect after the injecting the HPM is studied.The main content and results are as follows:1.Based on the Sentaurus-TCAD software,this thesis builds a model of CMOS NAND gate using 0.35 ?m process,followed by the mesh of the model.Using a numerical calculation model solved by a series of basic semiconductor physical equations,a high power microwave that can be approximately equivalent to an unattenuated the sine wave is modeled.Based on the model,this thesis does a research on the failure model including functional upset effect and failure effect when different ports(source,drain and gate)of CMOS NAND gate is exposed to HPM.2.For the upset effect,the theoretical and simulation results show that the internal PN junction of devices is under positive bias,resulting in current path in the substrate formed by the large number of carriers that causes the latch up effect,which leads to the abnormal function of NAND gate.For the failure effect,the distribution of electrical field strength,the current density and the temperature indicates that the cause of damage is the large amount of Joule heat caused by strong electric field and high current density which produces high temperature hot spots and causes the melting and burning of the NAND gate.The formation process of the latch path differs according to different injection ports.Besides,different HPM coupling and paths with distinct physical process and mechanism may lead to different damage of the device.The multi-port injection is studied other than the single port and the results show that the device are more prone to melting burned when the source and drain side is injected at the same time,and the source and substrate side being injected at the same time can reduce the disruption effect.3.Based on the analysis of the upset effects and failure effects along with their mechanism of CMOS NAND gate under HPM,factors influencing the upset effects are discussed.The change of upset effects of NAND gate at different temperatures is studied afterwards.The results demonstrated that the upset effect is very sensitive to temperature.In the studied range of temperature,the easier the upset effect tend to take place at higher the temperatures.The HPM signal duty cycle,pulse repetition frequency and N well depth of device influence on upset effect is also discussed.It is considered that when the pulse period is the same,the wider the duty cycle is,the more likely the upset effect is to happen.Higher repetition rate of pulse makes the accumulation more prone to happen and indicates smaller disturbance power threshold.The depth of the N well can increase the resistance to the upset effect.The mechanism of failure effect and functional upset effect along with its influencing factors of CMOS NAND gate under microwave injection discussed in this thesis provides a theoretical basis for the methods to strengthen and protect the high power microwave for semiconductor devices and digital integrated systems.