Research On The Damage And Upset Effects Of CMOS Inverter Induced By High Power Microwave

The interaction between increasingly complex electromagnetic environments and modern integrate circuit(IC)with scaling down feature size has become a hotspot in research area of electromagnetic pulse technology and microelectronic reliability,and high power microwave(HPM)is a typical source leading to electromagnetic environment with high power level,high frequency,fast speed and wide radiation scope,and gets increasing number of studies in the field of electronic information and military confrontation in recent years.HPM is able to couple into devices through various paths,i.e.antennas,apertures and air holes,results in intensive nonlinear effect on electronic systems such as temporary or permanent degradation in performance and failure in function even physical damage.On the other hand,as modern semiconductor technology advances and integrated circuit feature size scales down,the susceptibility and vulnerability of microelectronic circuits and components on external intentional or non-intentional electromagnetic increase,the demand on the anti-HPM design of electronic system gets more pressing.Therefore,it is urgent to study the HPM effect of electronic systems and semiconductor components systematically.This work focuses on CMOS inverter which is widely used in digital integrated circuit and develops a series of research on its HPM thermal failure and upset effect,and the main conclusive results are as follows:1.Using device simulation tool Sentaurus-TCAD,an N-well CMOS inverter based on 0.35μm technology under HPM is established and validated by static characteristic simulation.On the basis of solid heat conduction theory,a CMOS inverter temperature analytical model involving frequency and width under HPM is proposed,and then the variation trend of thermal failure threshold is obtained.The analytical model and threshold variation are validated and explained physically,and turns out that the Joule heat induced by forward current across “source-bulk” junction during negative semi-cycle leads to temperature rise,and the maximum temperature is positively correlated with width and negatively correlated with frequency.Moreover,the heat generation rate presents the same trend since PN junction current is positively correlated with temperature,consequently the thermal failure becomes larger with increase in frequency and decrease in width.The results obtained are consistent with experiment data reported.2.On the basis of established simulation model,the mechanism and influence conditions of another typical failure mode,function upset effect,are investigated.The results demonstrated that the latch-up path triggered by excess carriers injected and accumulated in substrate under HPM is the cause of upset.By deriving the relationship between latch-up trigger power and duty cycle,the increasing susceptibility under shorter-width pulsed wave is revealed,and the pulse repetitive frequency(PRF)effect is believed to due to the accumulation of excess carriers.An approach to improve anti-HPM performance by adopting deep well process is proposed.The latch-up delay phenomenon and correlated factors under low bias voltage are studied,and it is believe that one can reduce the supply voltage in order to resist HPM effect.An estimation method of circuits or systems’ HPM effect using behavior model is proposed.The mechanisms of HPM thermal failure and logic upset and variations of malfunction thresholds proposed in this paper provide theoretical bases and references for the HPM effect assessment and anti-HPM harden design in microelectronic devices,circuits and systems.