The Design Of BRAM Module In The High Performance FPGA

With the development of micro-electronics technology and the improvement of process, digital circuit has higher level of integration, Among which, field programmable gates array(FPGA) is used widely. It is the product that developed based on programmable array logic(PAL),erasable programmable logic device(EPLD) and so on. Now, FPGA has been used in the field of system design, such as aeronautics and astronautics, multimedia, military and so on. So we need amount of storage space and the design of the storage resources.The massive storage(BRAM) of FPGA is a configurable sram and has good configurability to meet various needs of user.After various research, this paper design a block memory module based on 130 nm CMOS process, embedded in the FPGA chip. It has a real double port and configurable properties. And each port supports 6 kind of data organizations,including 16Kx1、8Kx2、4Kx4、2Kx9、1Kx18 and 512x36.what is more, it has check digit and supports three kind of work modes(write first, read first and output keep).we adopt a structured and hierarchical design method to mainly complete the configurability of bits and low power consumption of the clock pulse control circuit. Dual port storage has the symmetrical circuit structure on both ends, including: the storage cell array made of basic storage unit according to the row and column; word line decode circuit from low seven address; bit line from high five address; timing control module; peripheral circuit module. We have done the part and overall function simulation.The significance of this topic is to break the monopoly of main FPGA technology in foreign and is important to realize the independent research and development on programmable device.It laid a solid foundation for the design of the product and manufacture.