Research On The Soft Error Rate Calculation For SRAM-based FPGA

With the rapid development of space industry,because of its repeatable programming,low power consumption and many other advantages,SRAM-based FPGA(Field Programmable Gate Array)are widely used.However,the high-energy particles in the space environment,such as ? particles,will cause sensitive SRAM cells to occur with single event upset,which can lead to soft errors and seriously affect the stability of space systems.Soft error rate is an important indicator of system reliability and guides the designer to carry out targeted protection to improve the overall system reliability.However,the hardware-based soft error rate estimation method will consume a lot of financial resources,and other software-based soft error calculation methods,such as Monte Carlo,are not suitable for large-scale FPGA design.In order to reduce the cost and adapt to the large-scale FPGA design,this paper systematically studied the hardware design method of FPGA,and gives the forward circuit diagram generation algorithm based on XDL(Xilinx Design Language)file,and puts forward a lightweight calculation method of soft error rate for SRAM-based FPGA.This method can simulate the soft error rate of FPGA design in ground experiment and space environment,and can meet the urgent requirement of assessing the reliability of space system in China,which is of great significance to improve the continuous operation capability of space system.The main work and contribution of this paper are as follows:(1)Analyzed the advantages and basic structure of FPGA systematically,and provided an important reference for the follow-up research work.Then summarized the programmable technology of FPGA,compared the advantages and disadvantages of each programming technology.Then,the design flow of FPGA is analyzed,and the XDL file is automatically generated.Finally,the design method based on VHDL(VHSIC Hardware Description Language)is analyzed,and the specific classification criterion is given,and the function modules needed for the follow-up work are obtained.(2)A set of XDL file automatic generation system based on FPGA design flow is proposed.First,the VHD(VHSIC Hardware Description)file of the function module and its attachment files are analyzed as system inputs.And then by analyzing the relationship of the attachment file and the current function module,PRJ files and XST files are automatically generated.Finally,by using the C++ development process under Linux,the XDL file is obtained by calling xst,ngdbuild,map,placement and xdl commands.(3)A set of forward circuit diagram generation algorithm based on XDL file is proposed,and the forward circuit diagram of function module is automatically generated by combining INST and NET contents in XDL.First,the node information of the function module and the information of the configuration bits in the node are analyzed from the INST part of the XDL.And then from the NET part of XDL,the information of the signal flow between nodes is obtained.Finally,the node configuration information and the node signal propagation flow are used to construct the forward circuit diagram of the function module.The method is theoretically applicable to all types of SRAM-based FPGA devices.(4)The soft error rate calculation model of the function module based on the forward circuit diagram analysis is given,and the calculation mechanism of the soft error rate is expounded from the aspects of the generation and propagation of the soft errors.Firstly,the sensitive configuration bits of each node in the forward circuit of the function module are analyzed,and the method of calculating the single event upset rate of the simulated ground experiment is proposed.The Node Error Rate(NER)is calculated by using the node sensitive configuration bit and the single event upset rate.Then,the propagation of soft errors in the forward circuit is analyzed,and the calculation method of Netlist Impact Probability(NIP)is proposed.Finally,the soft error rate of the function module is calculated by combining NER and NIP,and the correctness of the model is verified by the experimental results.In summary,the soft error rate calculation method of SRAM-based FPGA in this paper does not involve the actual hardware simulation,which greatly reduces the financial power consumption.In addition,based on the soft error rate calculation method of XDL file,this paper can carry out simple,direct and effective analysis for different scale FPGA design projects,which greatly improves the robustness of soft error rate calculation of SRAM-based FPGA.Finally,a summary of the work of this paper,and pointed out the follow-up work plan.