Study On The Read/Write-disturb Issue In Embedded Dual-port SRAM

The embedded Static Random Access Memory(SRAM) is an important part of modern SoC; With the advance of the manufacturing process, the study on SRAM never stops. Dual-Port SRAM(DP-SRAM) can provide the system with a higher communication efficiency and parallel computing capability. With the enhancement of the system throughput, DP-SRAM becomes more and more popular.Aimed at the Read/Write-Disturb issue in DP-SRAM, the memory cell and peripheral circuits of the embedded SRAM are fully studied. The complete read/write operation process of SRAM is clearly described. The mechanism of the Read/Write-Disturb issue is analyzed, one instance of TSMC 28 nm DP-SRAM(TSDN28HPM) is simulated and a deteriorated write-disturb issue is found at 6σ variation of the process. A detailed analysis is further made, based on which a proposed word-line pulse control technique solves the problem.The main achievements of this paper are as below: Firstly, the flexible tracking circuits and the characteristic of sense amplifier in 28 nm embedded SRAM are given. Secondly, a write-fail caused by write-disturb in TSDN28 HPM is obtained by simulation and the clock skew dependency of the write-disturb is also simulated. Thirdly, a word-line pulse control strategy is proposed. The write-fail is resolved by controlling the assertion time and the width of the word-line pulse. Using the 28 nm HPM process of TSMC, the post-layout simulation is performed across all the design corners, which shows the method is feasible and effective.