Research On SEU Fault Tolerance Technology Of SRAM FPGA

SRAM-Based field-programmable gate arrays(FPGAs)are widely adopted in aerospace domains due to the high logic density and programmability.However,the SRAM cell based on the CMOS architecture is susceptible to the strike from ionizing particles in the space radiation environment leading to state change,namely single event upset(SEU).For smaller technology nodes in FPGA,the single bit upset(SBU)is easy to trigger multiple bit upset(MBU)because of provocating adjacent bits' s flip.Therefore,the fault tolerance research about MBU is of significance owing to the BRAM(Block RAM)and CRAM(Configuration RAM)on FPGA accounting for high proportions.The paper implements a diagnosis system with Xilinx XC5VFX70 T for SEU fault mitigation.MBU events are generated from injecting up to 4 error nodes to emulate common cases in real environment.Finally,MBU faults are repaired by improving the capability of error detection and correction(EDAC)system.It shows the effect of SEU can be minimized to the lowest limit and the reliability of FPGA operation can be enhanced.In this paper,in order to protect the BRAM operation on FPGA,Reed-Muller(RM)codes is applied to an EDAC fault-tolerant unit.Furthermore,because the EDAC unit is vulnerable to space radioactive environment,triple modular redundancy(TMR)is then combined to reinforce its stability and reliability.The frame organization structure is first analyzed,then the readback/configuration operation of the CRAM is performed by employing the internal configuration access interface(ICAP).Gray codes with the parity bits is applied to realize error detection and correction of configuration frame data.To reduce the amount of processed frame data,the essential bits related to user customized design in the CRAM are extracted as a fault library.Finally,the experiment results indicate that the SEU diagnosis system implements the error injection,detection and correction of BRAM/CRAM.In reflecting functional and timing behaviors of BRAM/CRAM,it is capable to correct error of 3bits or less.At a working frequency of 50 MHz,the error detection and corrention of CRAM operation can be completed.The time of the readback of a whole frame data plus the single-frame error repair period is 2.38?s,the reconfiguration period is 2.32?s,and the proportion of slice resources occupied by the customized system is about 2.7%.