Font Size: a A A

Digital Baseband Design Of UHF Passive Tag With Intelligent Dual Port Based On ISO 18000-6C Protocol

Posted on:2017-05-01Degree:MasterType:Thesis
Country:ChinaCandidate:Y H DongFull Text:PDF
GTID:2348330515467049Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Radio frequency identification technolog realize auto identification and data collection by using radio frequency signal.This technology has made rapid progress in the decade.It is widely used in all areas of life and makes daily life and work more intelligen.With the continuous improvement of radio frequency identification system,the use of this technology will be more extensive and diverse.The main research content of this paper is as follows: the digital baseband circuit design of the smart dual antenna electronic tag.This design is based on the ISO/IEC 18000-6C protocol,is a super high frequency passive RFID tag.Different from the traditional electronic tags have only one antenna,but with two antennas at the same time,both of them can collect radio frequency energy for powering the chip,and has the ability to smartly choose a communication antenna.The electronic tag with double antennas can improve the communication distance between itself and the reader,and can reduce the sensitivity of the direction.This paper complete the integration,optimization and verification of the RTL level code for the digital baseband circuit,and complete the logic synthesis process.Finally,the netlist is transformed into physical layout by physical design.The process of the design is UMC 0.18 um CMOS.Overall design based on low power design concept.The physical design flow of the design mainly includes: data preparation for physical realization,global planning in the premise of considering the actual situation of the design,placement,CTS,route,the whole design of different stages are based on the optimization of timing,power consumption and congestion.In order to guarantee the performance of the chip,after getting the layout of the design,static time analysis,physical verification,post simulation and so on are all employed to check the design.Finally,the chip meet the design rules and requirements.The final physical layout area is 920×920?m2,and the total power consumption is 253?W.
Keywords/Search Tags:RFID, Dual-antennas, Digital Baseband circuit, ASIC front end design, Physical realization
PDF Full Text Request
Related items