| Given its advantages of high speed in reading and writing,Static Random Access Memory(SRAM)is widely used in System-on-Chip(SoC).Moreover,recent years have witnessed the significantly increasing demand for low-power SRAM.The power consumption of SRAM includes both leakage power and dynamic power,and the former has become dominant with the advanced process nodes.Therefore,the design of low-leakage SRAM becomes more and more critical.In this thesis,a low-leakage SRAM that can be applied in mobile devices,IoT and deep learning processors has been designed using GLOBALFOUNDRIES' 7 nm process.This thesis starts from the presentation of system architecture with emphasis on the dual power system architecture which is applied to reduce the overall leakage power of SRAM,followed by the elaboration of multi-threshold techniques and deep sleep techniques which are applied to respectively reduce the leakage power of word line drivers and that of the memory arrays.Afterwards,this thesis proposes three techniques,i.e."fine-grained bit line stacking technique","floating write driver technique" and "bank-level power-gated word line driver technique",designed to respectively reduce the leakage power of the sense amplifier,write driver and word line driver.Finally,this thesis designs the layout of SRAM and accordingly performs behavior-level verification and functional verification.The behavior-level verification achieves a verification coverage rate of 97% by designing an input pattern.The functional verification verifies the SRAM's read and write functions,scan chain functions,and deep sleep and data retention functions using simulation.The post-simulation results show,compared with the traditional structure,that the leakage power of SRAM is reduced by 75%,while the area is only increased by 1.5% with the performance degradation of 13%.This SRAM works well at supply voltage ranging from 0.5V to 1.2V,and,specifically,it is able to work on a frequency as high as 2GHz at 0.9V. |
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