The Research And Implementation Of Embedded SRAM Techniques In 65nm Technology

Static Random Memory (SRAM) as one kind of critical memory is widely used to CPU high-speed caches and System-on-Chip (SoC). As technology feature size scales down, the density of chip is constantly increasing. The developing trends of memory come to high-performance and mass storage. The increasing of capacitance leads to the increament of delay while accessing SRAM, as well as leakage power. Therefore, the design of high-speed and low-power SRAM becomes an important theme.This paper is about the design and optimizes of embedded SRAM techniques in 65nm technologies. Based on the application requirement of SRAM for DSP chip, we research with emphasis on the design and implementation of mass storage SRAM and dual-port high-speed SRAM, as well as low-leakage technique in SRAM which depresses the memory's leakage power. The main contributions are as follows:1. In the design of mass SRAM, we plan to implement a 1MB 600MHz L2 Cache. We make a optimization to the division scheme of whole layout structure to every module circuit. After a compare of the performance among three memorys, we get an optimization memory that is 4096x32, with which we use to build L2 Cache. In the analysis of IO circuit in mass SRAM, we rearch with emphasis on sense amplifier and promise an improved amplifier with leakage control, which depress the reading delay about 30.364ps.2. To achieve the design purpose for high-speed SRAM, we promise the particular policy in read-write and encode in the design of dual-port high-speed SRAM. After the verification of timing and function to the memory in full custom design, we find that the data output delay and power of SRAM reduce by 22.7% and 10.5%, while comparing with SRAM build by Memory Compiler. Then SRAM can work normally in high frequence up to 1.2GHz.3. In the research of low-leakage in SRAM, we firstly analysis memory array, in which we research the principle of lowing leakage in three kind of structure, independent division bulk and bit-line division and word-line pulse. Then we make analysis of leakage of memory cells to reduce the leakage. One instance is that we promise a new low leakage technology using virtual supply in 7T cell.