Research Of Low Power Design And Optimization For CMOS Circuit

The development of integrated circuit industry increases CMOS circuits operating frequency and integration, but it also brings the rise of circuit density. As the technology feature size decreases, the circuit power consumption rises in an exponential way. High power consumption reduces the stability and reliability of the circuit system, meanwhile, makes it difficult packaged. Thus, the low power design is increasingly becoming an important part of the current circuit design.CMOS circuit industry keeps developing and being towards the deep submicron industrial node, so static power of transistor can no longer be ignored and must be taken into account in the circuit design. The paper explains the power of the CMOS circuit and presents an improved algorithm based on dual-threshold low power technology. It also puts forward a new design of D flip-flop,using dual-threshold low power devices. The main content of the thesis includes:1.Research of dual-threshold algorithm on timing path. After deep analysis of the algorithm and building the circuit model, the paper puts forward the improved algorithm based on the WNS and modified TNS of circuit nodes. Each node will be selected more appropriately and fewer LVT cells will be selected.2.Research of D flip-flop optimization. The D flip-flop is optimized based on the dual-threshold idea, and the clock response circuit performance is highly improved. The clock toggling is controlled by data signal, simply to clock gating. This design is good for reducing clock toggling and dynamic power consumption, and has a remarkable effect.