Resarch On Low Power All-Edges-Triggered Flip-Flop Design

Nowadays, the digital signals in the predominant IC are the binary signals of the least information capacity, which results in the main drawbacks of IC that the interconnections and pins are excessive. In addition, CMOS technology will be confronted with fundamental physics limitations in its scaling of process, such as heat dissipation problem, short-channel effects, quantum tunneling and high leakage power. Meantime, nanoelectronic devices of next-generation are being developed, such as neuron-MOS (vMOS), resonant tunneling devices (RTD), quantum-dot cellular automata (QCA). These devices are often of multiple states and could play a better device in multivalued circuits, rather than binary circuits. In order to settle the main drawbacks of IC and make full use of the next-generation devices with multiple states, more concerns should be put on multivalued circuits. Multivalued flip-flops are the basic element and design key of multivalued circuits.Moreover, with the rapid development of CMOS technology, the scale and density of integrated circuits (IC) are increasing greatly, its clock frequency getting constantly higher as well. This leads to the rapid increasement of IC power dissipation, so the power reduction becomes incrucial in circuits design. The power dissipation of the clocking system, including clock distribution networks and flip-flops, is often the largest portion of the total chip power consumption. In order to reduce the power dissipation substantially, this thesis applies multivalued clocks to sequential circuits as an effective way to the power reduction.Upon the points above, the thesis proposes a low-power multivalued all-edges-triggerred flip-flop based on multivalued clocks, so the following works are carried out.Firstly, the thesis makes a thorough investigation into multivalued clocks. According to the principle making full use of multivalued signals, a standard waveform of multivalued clocks is determined. A way of power estimation for multivalued clocks is analysed according to the practical application of multivalued clocks. In addition, some characters of multivalued clocks are found out, such as its odd-even switchs.Secondly, multivalued clocks generator is a shortage nowadays. For the practicity of the informative multivalued clocks, the thesis designs a ternary clock generator (TCG). Its HSPICE simulations with CMOS technology show that it works properly. The analyses show that the TCG is simple and works effectively, so the TCG meets the clocks design requirements.Thirdly, for an easy design of any radix flip-flop based on arbitrary radices clocks with a simple structure, this thesis designs the latches based on multivalued clocks and analyses its working principle. Combining the latches principle with the switch rule of multivalued clock values, this thesis proposes a general structure of multivalued all-edges-triggered flip-flop (AETFF) based on multivalued clock. The highlight of AETFF is that it is suitable for any radix flip-flop design and also sensitive to every edge of arbitrary radices clocks, reducing the clock frequency and power dissipation for no redundant edges.In order to validate the general structure, the thesis implements CMOS binary and ternary AETFFs based on ternary clock, namely quad-edge-triggerred flip-flops (QETFF), and CMOS quaternary AETFF based on quaternary clock (Q-AETFF-Q). The simulations validate they can all work properly. Furthermore, the binary and ternary QETFFs consume12.5%and9.5%less energy than the equivalent flip-flops, respectively; Q-AETFF-Q takes the first place in the joint structure-functionality metric among CMOS flip-flops.The general structure not only facilitates the design of any radix AETFFs based on arbitrary radices clocks, but also can be used to the design of multivalued flip-flops using next-generation devices. This will make contributions greatly to practical application of multivalued circuits.