| Over the past decades, we have experienced a phenomenal growth of the binary- based VLSI technology. Although the scaling approach has been so successful so far in enhancing the capabilities of silicon chips, the number of transistors or functions implemented on a chip have been ever-increasing and the physical dimensions of transistors have been continuously scaled down ,a number of severe limitations are now being encountered in terms of power consumption, number of interconnections, cooling of devices, material properties, performances of miniaturized devices, and design of VLSI circuits and systems. The electric field strength in scaled-down devices is now approaching the limit of intrinsic material properties, imposing severe limitation on the circuit performance. In order to keep the growth trend of IC technology, and develop the potential of fabrication process, new devices or design conceptions should be broken through. The multiple-valued logic and neuron-MOS transistor do.First, this dissertation describes the basic conception of MVL and neuron-MOS. Because of the particularity of the new device, an equivalent model for it is proposed. Then, based on the principles of vMOS—DLC and C-vMOS source-follower circuit, a new design configuration of multi-valued combinational circuits is presented. Guided by the proposed configuration, a serial of multi-valued circuits are designed, and on this basis, we analyze and discuss the configuration in detail. Finally, clock-controlled neuron-MOS is introduced. Based on the theory, a new design for D-type latch is proposed, which then is used to design a multi-valued D-type master-slave flip-flop and a 4-bit asynchronous 4-value counter. Performance of all the proposed circuits are evaluated using HSPICE simulations with AMI 0.5μm CMOS process. Simulation results show that the logical functions can be realized accurately by these circuits. Moreover, the configurations are simplified dramatically, and very flexible. |
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