The Flip-Flops Of ECL And Current-mode Cmos Design Based On Threshold-Arithmetic Algebraic System

With advantage of high speed, small distortion, low power consumption, low supply voltage, strong anti-interference performance and be easily implement arithmetic operations, such as addition, subtraction, multiplication, the current mode circuits are getting more and more attention. Emitter-couple logic (ECL) circuits can operate at high switching speeds, because of the unsaturated transistors eliminating the transistor memory time, and the power dissipation of ECL circuits remains constant as frequency increases. So ECL circuits have often been employed in very high speed VLSI circuits. It is well known that the voltage signals of ECL circuits depend on internal current signals operation. In this paper ECL circuits are considered as current mode circuits to be designed.Based upon the fact that the current signals are easy to add or subtract by simply tying wires with each other, we have proposed the threshold-arithmetic algebraic system (TAAS) for current-mode circuits design. TAAS is composed of threshold-arithmetic operations, arithmetic operations and nonnegative operations, acting as the basic operations of TAAS, and the HE Map in this system is expressed for threshold-arithmetic functions as Karnaugh Map for logic functions. TAAS has been applying in current mode combinational circuits design. It provides a directly, simple and effective methodology for current mode circuits design, but not in current mode sequential circuits. Flip-flops, as the basic unit of sequential circuits, play a crucial role in the design of digital integrated circuits. High-performance flip-flops have been an important part of the digital system design. Therefore, utilize the TAAS to design flip-flops circuits, has important theoretical significance and practical value.Firstly, based upon the characteristics of ECL circuits and TAAS, this paper proposed the methodology of ECL combinational circuits design. With this methodology, the binary logic and multiple-valued logic ECL circuits are designed. And based upon the methodology of ECL combinational circuits, a methodology of ECL flip-flops design is proposed. The binary logic and ternary logic ECL D latch and ternary logic ECL T latch have been designed. Upone the proposed latch, the binary logic master-slave ECL D flip-flop are designed, and the ternary logic ECL D and ECL T flip-flop can be designed.Secondly, with the requirements of pulsed-triggered flip-flop and the threshold-arithmetic algebraic system, an novel universal structure of current-mode CMOS pulsed-triggered D flip-flop was proposed for binary and multi-valued current-mode CMOS pulsed-triggered D flip-flops design. Based on the proposed structure, a binary current-mode CMOS pulse-triggered D flip-flop (BCMPDFF), ternary current-mode CMOS pulse-triggered D flip-flop (TCMPDFF) and quaternary current-mode CMOS pulse-triggered D flip-flop (QCMPDFF) were designed, and the designed flip-flops can be easily incorporated into single and double edge-triggered design.HSPICE simulation using TSMC180nm CMOS technology has shown that the designed circuits have the correct logic function. The accurate results of simulation confirm the validity of the proposed methodology. This paper proposed a directly, simple and effective methodology for ECL circuits and current-mode CMOS flip-flop design. And the designed circuits have the advantage of fewer transistors, relatively simpler structure and higher performance.