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Design On Fpga Based High-Speed Data Acquisition And Transmission System

Posted on:2015-06-21Degree:MasterType:Thesis
Country:ChinaCandidate:S C XuFull Text:PDF
GTID:2298330467463788Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
With the rapid development of information technology, people are more eager to get data quickly, from which to extract useful information precisely. In many fields, data acquisition and transmission system has its important applications, and plays a fundamental system role. This thesis uses FPGA as the main control device in hardware implementation, realizes the main interfaces used in the system construction, and designs a complete real-time data acquisition and transmission system.For the ADC/DAC interface, the thesis introduces how to connect FMC150daughter card with FMC standard, including how to design SPI interface, how to leverage FPGA’s OSERDES、IDDR primitives etc. to send and receive data.For the Ethernet interface used for data transmission between host and target board, the thesis illustrates how to adopt CORE Generator tool to wrap and customize V6EMAC. Then we program the upper computer program based on WinPcap, thus connecting the target board to the host.As to the DDR3SDRAM used to buffer high-speed data, the thesis illustrates how to leverage MIG tool of XILINX co. to wrap and customize this interface, then illustrates how to simulate and verify the interface.At the end of the thesis, we describe how to realize the phase compensation module in coherent optical communication system. After analyzing the root causes of phase jitter, we realize the phase compensation function based on FPGA. The experiment result shows that the phase stabilization method our project group come up with can ideally compensate for phase jitter resulting from environment factors.The design presented in the thesis adopts module level and system level functional and timing simulation and performance test, making it running stably. The result shows that, the right design and basic functions can meet the demands of high-speed real-time data acquisition and transmission system, laying a solid foundation for building advanced system based on this point-to-point transmission system in the future.
Keywords/Search Tags:FPGA, high-speed transmission, phase compensation, DDR3, ADC, Ethernet
PDF Full Text Request
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