.10-40gb / S Optical Communication And Gigabit Ethernet High-speed Data Decision Chip Design

In recent ten years, the technology of LAN and optical transmission has achieved revolutionary advancement with the development of the telecommunication technology, researches on optical transmission ICs and 10 Gbit/s Ethernet become more and more heated.Super-high speed data decision chip was used widely in the clock and data recovery(CDR) module of PMA layer in the Ethernet or of optical transmission systems. The performance and speed of the chip always determined the specifications and speed of the systems. The chip was widely realized by Master-Slave D Flip-flop, which was core cell of all kinds of digital circuits and key module of MUX/DEMUX of the PMA layer in the Ethernet or of optical transmission systems. Therefore, the research and develop of the chip hold the balance.The constitutes and fundamental theorem of CDR circuit were first introduced. After discussion of the data decision, the several structures of data-decision circuits used by D flip-flop were analyzed. Due to particularity of super-high speed IC design, the design technique for high-speed and high-frequency IC was introduced afterward, mainly about matching technique, the parasitic model of interconnect and the behavioral analysis of transmission line, high-frequency compensation technique involved in the design.The circuit design was a important part of this paper, furthermore, it was core of super-high speed data-decision circuit design. The speed,size,power was common factor considered in the design, in addition, the specification of data-decision circuit design, such as: operation speed range, sensitivity of decision, phase margin and output phase offset, was taken into account. Every circuit structure has its merits and drawbacks, so the 0.18um CMOS data-decision IC for Gigabit-Ethernet, data-decision IC with 90o tuned phase-shifter designed for 10-Gigabit-Ethernet, and 40 Gbps super-high speed data-decision IC ( i.e., data-decision IC with HLO structure and super-dynamic structure ) were discussed in detail. The layout design was a crucial step in the design of whole chip, especially it affected the performance of high-speed IC. The essential factor of layout design was discussed briefly accordingly. In the end, the simulation results and test waveforms of all chips were presented and its performance,specification was mentioned.This project is supported by the "The National High Technology Research and Development Program of China (863 Program)", and the project of up and down interface chip research of 10 Gbps Ethernet physical layer has been successfully checked and accepted by the specialists.