The Research And Design Of Column Parallel ADC With Digital Double Sampling For CMOS Image Sensor

Compared to CCD image sensor, CMOS image sensor is widely used in imagecapture devices because of its low cost, low power and small cubage. The columnparallel ADC applied in CMOS image sensor could achieve a good tradeoff amongframe rate, fill factor, silicon area and power consumption. Therefore the columnparallel architecture is the most widely used for imager. Generally, the signal frompixel needs to be processed with double sampling before being quantised.In this paper, based on the analysis of column parallel readout circuit, the analogcorrelated double sampling circuit and the digital double sampling circuit are designed.The architecture and principle of analog correlated double sampling are analyzed first.Offset cancellation technique is used in the circuit to eliminate the offset of theamplifier. The gain is modulated by changing the capacitance. The designed circuitcould achieve function by simulation. The analog error caused by parasitic conpacitorand finit gain would be accumulated. Then based on the single-slope ADC, a10bitscolumn parallel ADC with digital double sampling is designed. Offset cancellation isused in the comparator; and the up/down ripple counter realizing digital doublesampling digitally subtracts the conversion of the reset signal from the sensor signal.So the error caused by offset and finite gain of amplifier in analog circuit could beeliminated. The error caused by delay of comparator could be reduced. Bandgap andcharge pump are designed in this paper, as well.The circuits are designed and simulated in GSMC0.18μm standard CMOSprocess. The analog correlated double sampling circuit could achieve the function.The sample rate of the column parallel ADC with digital double sampling is45KS/s,the signal-to-noise ratio is60.17dB, the signal-to-noise and distortion ratio is53.98dB.The designed bandgap and charge pump could achieve the function, as well.