Research On The Key Techniques Of High Performance Column Readout Circuits For CMOS Image Sensors

Ultra-high-definition photography,virtual reality,augmented reality,autonomous driving,machine vision,etc.applications demand large-pixel-resolution,high-framerate and high-dynamic-range complementary metal-oxide-semiconductor(CMOS)image sensors(CISs).Consequently,fast-speed and high-resolution readout circuits are required.The column readout schemes compromise speed and resolution.They are suitable for high-speed and high-resolution applications.The speed and resolution of a successive approximation register(SAR)analog-to-digital converter(ADC)are moderate.It can fulfill the requirements of column readout circuits for CISs.It also features simple architecture,low power consumption and easy implementation in submicro processes.However,with increasing resolution,the number of capacitors and the capacitance of the unit capacitor in a SAR ADC grow exponentially due to capacitor mismatch and sampling noise requirements.To alleviate these problems,some corresponding techniques for the architecture,mismatch calibration and sampling noise reduction are analyzed in this dissertation.By using these techniques,SAR ADCs can be effectively used in column readout circuits for CISs.To reduce the number of capacitors,a two-step(TS)scaled-reference(SR)SAR ADC is adopted.A 7-bit capacitor digital-to-analog converter(CDAC)and two SRs are used to achieve 14-bit resolution.The CDAC can resolve the upper 7 bits with two external references,and the lower 7 bits with two SRs.To obtain accurate SRs,SR calibration circuits by using a TS SR SAR ADC are proposed.A correlated double sampling(CDS)programmable gain amplifier(PGA)is used to convert a single-ended unipolar pixel signal to a differential-ended bipolar form for the differential-input ADC.An intentional offset is set to prevent the readout circuits from saturating in the dark environment.These column readout circuits are integrated into a CIS with 190H×160V pixel array and 3000 frames per second,and verified in a 180 nm CMOS process.The measurement results show that the signal-to-noise ratio(SNR)of the ADC is 73.90 dB and the CIS can capture images as expected.For the TS SR SAR ADC,capacitor mismatch and SR errors limit the capacitance of the unit capacitor to be smaller.To reduce the capacitance,a TS SR redundant 14-bit SAR ADC based on a redundant CDAC and redundant SRs are proposed.The weights of each capacitor and each SR can be extracted by calculating the output digital code histogram with a foreground calibration algorithm,which is realized by the back-end of a CIS system.It needs no extra hardware overhead within the chip.A sub-radix-2 CDAC and larger-than-theoretical-value SRs are used to ensure redundancy.To remove the most significant bit(MSB)capacitor,a hybrid CDAC switching scheme,which combines a common-mode voltage based switching scheme for the upper bits and a conventional switching scheme for the lower bits,is adopted.The minimum size metalinsulator-metal(MIM)capacitor from the process is used.This ADC is verified in a 180 nm CIS process.The measurement results show that the integral non-linearity(INL)and the effective number of bits(ENOB)of the ADC are improved from +21/-21 to +2.3/-2.5 LSB and from 8.83 to 11.10 bit,respectively.By applying redundancy and calibration to a SAR ADC,the capacitance of the unit capacitor can be reduced to the sampling kT/C noise limitation.To further shrink the unit capacitor,a kT/C noise-reduction sampling circuit with a two-stage amplifier is proposed.The noise bandwidth(BW)is reduced by the sampling circuit while the noise power density(PSD)is almost unchanged.A switching bandwidth technique is used to keep the tracking accuracy and power consumption to be almost the same as a conventional sampling circuit.A 12-bit SAR ADC with this noise-reduction sampling circuit is verified in a 40 nm CMOS process.The capacitance of a single-side CDAC is reduced to 132 fF.The measurement results show that 71% sampling kT/C noise power is reduced,comparing with a two-stage amplifier active sampling circuit without noise reduction.