Research And Implement Of Topology-aware Floorplanning For3D Application-specific Network-on-chip Synthesis

As the technology scaling, System on Chip (SoC) design is becomingmore and more complex where more processors and memory componentsare integrated into one small chip. Network on Chip (NoC) has beenadvocated as a new design method for addressing the challenge of SoC.Compared with the traditional bus-based interconnection architecture, thescalable and modular nature of NoCs supports it as the inevitable directionfor the multi-cores design in the future.Moreover, NoC topology has a great influence on the performance ofthe system. Unlike regular NoCs (like mesh or torus topology),Application-Specific Network on Chip (ASNoC) has bothcustom-designed topology and NoC components. NoC components aremainly switches and network interfaces (NIs). Therefore, forApplication-Specific SoCs design which consists of heterogeneous coresboth in sizes and functions, ASNoCs have been proved to be superior thanregular NoCs in terms of power, area and performance. Besides, it’s anecessity to design an efficient Network-on-Chip (NoC) topology with thetechnology of three dimensional integrated circuits (3D-ICs) that isemerging as a promising solution to address the challenges in SoCs.For the3D ASNoC topology synthesis methodology, we propose atopology-aware floorplanning method to determine the power-performanceefficient topology.In previous works, the placement of the cores and networkcomponents, and the path allocation are explored separately. However, the path allocation strongly depends on the placement of cores and networkcomponents. Consequently, in this paper, we design asimulated-annealing-based methodology that integrates the separate steps(the clustering of cores+the placement of cores and switches+the pathallocation+the TSV-aware topology evaluation) within the3Dfloorplanning procedure. Through utilizing the information of topology(switches’ positions and communications) it adjusts the topology graduallyduring the floorplanning. Obviously, the combination of the local optimalsolutions from the separate steps may be far away from the global optimalresult of the NoC topology, this topology-aware algorithm should findbetter global result.Several typical SoC benchmarks have been tested and the results of3D ASNoCs’ floorplan architecture show the effectiveness both on powerconsumption and latency.