Research On Techniques Of Application-Specific Processor And On-chip Communication Architecture Design

High-performance SoC (System on a Chip) have been playing an important role in multimedia applications especially the video compression which is everywhere in human beings' daily life. Application-specific SoCs (ASSoC) can achieve a good tradeoff between the flexibility of general-purpose computing platform and the performance and the efficiency of ASICs (Application-Specific Integrated Circuits). It is now the hotspot of research both in academy and industry. This thesis mainly focuses on design of Application-specific Instruction Set Processors (ASIP) and on-chip communication architectures, which both are critical technique in ASSoCs.As the core component of AS-SoC, ASIPs provide high computation performance while maintaining the flexibility as a programmable device. A video-oriented ASIP design is introduced in this dissertation. It utilizes the novel hybrid SIMD (Single Instruction Multiple Data) and VLIW (Very Long Instruction Word) architecture with the EDO (Explicit Data Organization) enhancement. Data permutation and re-organization functions are explicitly designated in the instruction encoding instead of extra permutation instructions which can significantly reduce the code size. Design of split ALU (Arighmatic Logic Unit) and the IFU (Instruction Fetch Unit) which supports variable-length instruction encoding are introduced. An instruction buffer is embedded in IFU that can significantly reduce the main instruction memory access.An application-specific instruction synthesis approach is also proposed in this dissertation. The application is first converted to directed data flow graph and a search algorithm is then applied on it to extract optimized instructions. This approach has been applied in the design of the mentioned ASIP. The instruction and data path optimization targeted at the in-loop filter of H.264/AVC is elaborated with the modification of the reference code for the improvement of parallelism.As more and more components are integrated into single chip, the data communication between components is now in the critical path of AS-SoC design. To model the communication of the target application accurately, a new abstract level called CEAM (Communication Event Accurate Model) is proposed and the data communication of the H.264/AVC has been modeled and simulated in CEAM. The profiling data is gathered during the simulation and an application-specific bus scheduling scheme is designed based on these data. The results of experiments show that the proposed scheduling scheme has a significant performance improvement against the general-purpose schemes such as RR (Round-Robin) an FP (Fixed Priority).