Studies On Key Technologies Of Networks-on-Chip Interconnection For Very Large Scale Chip-multiprocessors

Along with the development of device, process and application technology, the scale of chip-multiprocessors has been increasing, bringing in great challenges to network-on-chip, which constitutes the connection and communication subsystem of chip-multiprocessors. With regard to the inter-communications in the large and very-large scale chip-multiprocessors, this paper studies on the topologies of network-on-chip, and the structures of on-chip routers as well as traffic models.This paper makes the following contributions.1 A novel, simple and scalable network-on-chip router is proposed. The router, by bufferring data only in the output ports rather than in both input and output ports, cuts down the total number of buffers in the network-on-chip half with simplified hardware structures. Not only the area for the network-on-chip but also the count of buffer reading or writing on communication is reduced. Therefore, the transmission speed is increased while power consumption reduced. A customizable network-on-chip simulator has been designed and implemented. The simulator is well structured, flexible and scalable.2 A kind of local uniform random traffic model based on region division, LUR in short, is presented, with regard to the features of on-chip communication and the tiled structures of chip-multiprocessors. The LUR model is a generalized pattern of the uniform random traffic model, subsuming the latter as a special case. The LUR model matches well with locality characteristics of communications in chip-multiprocessors. Therefore, it is more accurate to simulate the on-chip communications in the large and very-large scale chip-multiprocessors with the LUR model than with the uniform random traffic model.3 Two novel structures, 2-D triangle and hexagon grids, based on the extension of 2-D mesh grid, as well as a kind of hierarchical network-on-chip topology and routing algorithm based on the Karnaugh map coding are proposed. A formal description on the relationship among various interconnection structures is presented. The characteristics of two extension grids and the hierarchical topologies are discussed. We show that the single-hierarchical ring based on the Karnaugh map coding is an idea structure for the on-chip interconnection in the large or very-large scale chip-multiprocessors due to its simplicity, low cost as well as fast transmission.4 A kind of novel network-on-chip with command transmission separated from data transmission is proposed, with regard to the different requirements for the commands transmission and the data transmission in chip-multiprocessors and the characteristics of different topologies in the large and very-large scale. A prototype to this novel network-on-chip named HHSR is presented, which transfers commands in single-hierarchical ring and data in 2-D hexagon mesh grid. The prototype guarantees and improves the transmission speed of the commands so as to guarantee and improve the performance of the whole chip-multiprocessors.