The Processor Design Based On The Scalable System-On-Chip

Since 1990’s, integrated circuits have developed rapidly. Integration level is getting higher than ever. A single silicon die is capable of integrating micro-controller, digital signal processor, accelerator and other cores together to form the system level chip, called system-on-chip(SoC). With the increasing of the complexity of SoC, the design cost and system performance is more and more restricted by inter-cores communication capability. The network-based interconnection performs better than the bus-based interconnection. Meanwhile, with the development of wireless communication system, several generations of technology evolution emerge, which lead the co-existing of multiple communication standards. On this occasion, hardware defined radio can’t satisfy the demands of multi-mode systems. The software radio allocates more signal processing tasks to processors. Thus the system can be implemented based on the network-on-chip(NoC) infrastructure for the purpose of communication signal processing. Most of the tasks of the system will be completed by processors or accelerators. This thesis designs some application-specific processor cores, and implements a scalable So C with these cores.By deeply analyzing the key algorithms of the 4th generation standard-Long Term Evolution(LTE), we design a scalar processor based on Reduced Instruction-Set Computer(RISC) architecture and the programmable Fast Fourier Transformation(FFT) coprocessor. In addition, we also design the programmable data-packing coprocessor to make the transformation between the processors and the on-chip networks. The processors are designed in accordance with the design flow of an application-specific processor. After analyzing the computation features adequately, instruction-set is designed. The Electronic Design Automation(EDA) tool and the Architecture Description Language are used to model the processors and generate Register Transfer Level(RTL) codes finally.The RISC-based processor is a 32-bit processor, whose instruction set is extended to contain instructions for hardware loop, interruption response, MAC(multiplication and accumulation), integer division, Turbo encoding and so on. This thesis describes the procedures of this processor and the micro-architectures of some key instructions. The instruction set of the programmable FFT coprocessor is designed according to the FFT computation features, and then the hardware architecture is designed. This coprocessor has the ability to compute the FFT with the available length from 16 to 2048. The programmable data-packing coprocessor is designed to assist the data exchange between the network and processors attached on it. At last, the RTL codes of all processors and coprocessors are generated to implement the scalable SoC on the NoC platform, and the functions are verified and analyzed.