Topology Generation And Floorplanning For Application-specific 3D Network-on-chip

As a new on-chip interconnecting structure, Network-on-Chip(NoC) architecture has advantages of high bandwidth, great scalability and low power consumption, and becomes an effective solution to overcome the problems of global interconnection and communication in complex So C design. The advent and increasing viability of 3D silicon integration technology make it possible to scale NoC over the third dimension. 3D No C improves the performance of the system. Combined with the design-specific characteristics in No C, the thesis carries out the research on the topology generation and floorplanning in 3D NoC design.The topology generation and floorplanning problem in 3D No C design is devided into three levels, including IP core layering and floorplanning, routers and nerwork interfaces insertion and path allocation. Firstly, considering the IP core communication relation and size information, a method based on B*-tree structure is proposed to divide IP cores into different layers in a 3D structure and obtain the optimal positions of IP cores. Then with the area of of routers and network interfaces taken into consideration, a model is proposed to obtain the optimal position of routers and networks based on genetic algorithm. We present a router merging algorithm to make the power consumption on links and chip area better under the TSV number constraint. Finally path algorithm based on Dijsktra and TP constraint is carried out to generate a deterministic deadlock-free minimal routing path for each communication trace of given application and balance the traffic across the links,and determine routers connection structure. Experimental results show our algorithm saves 32.5% of power consumption on links and 3.6% of chip area on average compared to the random results.In this thesis, the NoC simulator Nirgam is expanded to support irregular-topologies modeling and simulation. The NoC simulator is designed to simulate our proposed 3D NoC topologies on several multimedia benchmarks. Experimental results show that our proposed 3D NoC topology saves 66.2% of router numbers, 47.16% of chip area, 33.6% of communication latency, 65.6% of power consumption on router nodes, 65.4% of power consumption on links and increases 8.2% network throughput compared with regular 3D Mesh topology.