Research On Key Technology Of Application Sepcific Network On Chip Design

System on Chip (SoC) grows in size with the advance of semiconductor technology enabling integration of dozens of cores on a chip. The continuously increasing number of cores makes on chip communication architecture design encounters more complex problems, such as throughput, latency, power, signal integrity and clock synchronization. Traditional bus-based interconnect architectures are inherently non-scalable, making communication a bottleneck. Using data packet transmission scheme, Network on Chip (NoC) provides effective, reliable and flexible infrastructures for system modules, and becoming an effective solution to overcome the problems of global interconnection and communication in complex SoC design. Application-specific NoC is necessary because chip design has constraints of area, power and performance, and design methodologies for application-specific NoC is needed. In this thesis, we study on the key technology of application-sepcific Network on Chip design, and mainly focus on the simulation modeling and performance evaluation of NoC Architectures, IP cores mapping and routing path allocation, application-specific topology generation and routing scheme design. Our work sets an important basis for building complete design methodologies for application-specific NoC.We firstly propose a modeling and simulation approach based on OPNET from the perspective of system-level design, to evaluate performance of various NoC architectures by varying the network topologies, swiching techniques and routing algorigthms and simulate each of these under different injection rates and traffic patterns. Detailed comparative analysis of the simulation results in terms of average latency and throughput is presented, which could be used as a guideline for NoC designers to make appropriate choices for a given application in order to achieve optimal performance. To further illustrate our evaluation approach, we map a MPEG4 decoder application onto different NoC architectures and show their impact on the NoC system performance.A NoC co-mapping algorithm for minimizing the overall communication power consumption is proposed, based on the analysis and building of the NoC communication power model. It automatically maps IP cores onto NoC architecture combining IP selection and task assignment. The experiments performed on various random benchmarks and a complex video/audio application to confirm the efficiency of the algorithm. Experimental results show that the proposed algorithm saves about 30% and 60% of power consumption compared to the existing two-step mapping and only IP cores mapping algorithms on average. To slove the problem of communication path allocation between cores in NoC mapping, we difine the link-balance model, and present a genetic algorithm based mapping and routing approach called GAMR. GAMR generates a deterministic deadlock-free minimal routing path for each communication trace of given application, so as to minimize total communication power consumption and balance the traffic across the links under bandwidth constraint. The evaluation performed on various multimedia benchmark applications confirms the efficiency of the proposed approach. Experimental results show that GAMR saves about 20% of energy consumption and 30% of link bandwidth requirement on average compared to the existing NoC mapping and routing algorithms.Aiming at the problem of using regular topologies in application-specific NoC design, which may lead to large-scale redundant routers, lower link utilization or local congestion, we further research on application-specific NoC topology generation approachs. Based on the idea of NoC mapping and routing, a genetic algorithm based hierarchical topology generation approach called GATG is proposed. The aim is to reduce the network communication power consumption and resources cost. Under the constraints of the bandwidth and latency, GATG automatically maps IP cores onto the selected routers according to the communication requirements of given application and characteristics of router architectures. In addition, a recursion based routing path construction algorithm embedded in GATG is proposed to construct links between routers, and finally the application-specific irregular NoC topology is formed. Experimental results show that GATG achieves 45% of energy saving on average in comparison with using regular 2D Mesh topology, and also can obtain significant network resources improvement. Furthermore, we present a clustering-based topology generation approach for application-specific NoC. It simplifies the realization of GATG and reduces the complexity of the algorithm, and also can obtain better results in the area of communication power consumption and resources cost.Finally, from the perspective of the global communication management and reliability design in NoC, we has introduced the concept of network monitor, which monitors overall network real-time conditions and implements path allocation algorithm. Based on the network monitor, a novel dynamic routing scheme called DyRS-NM is presented for NoC application. The proposed scheme DyRS-NM has the ability to discover and deal with both congestion and permanent faults and distinguish them from transient faults. DyRS-NM can avoid transient faults by using retransmisson scheme, and also can detour congested and permanently faulted links by recalculating routing paths. This scheme sloves the problem of network congestion in heavy load, and improves the network throughput and fault tolerance ability. We have finished the circuit design of the network monitor and fault-tolerant router, and built the RTL-level model of network monitor based 4×4 mesh NoC architecture. The system performance and cost of area and power consumption is analysed. Compared to both static and dynamic XY routing, significant performance improvements can be achieved by using the DyRS-NM scheme with acceptable additional cost.