Dynamically Reconfigurable Topology Generation Methods For Application-Specific Network-on-Chips

With the development of semiconductor process technology,the number of IP cores on a chip has grown rapidly,and the traditional bus-based communication architecture cannot satisfy the performance demands of System-on-Chips(SoCs).In recent decades,Network-on-Chips(NoCs)have been proposed as a promising solution to address the global communication challenges in SoCs because of their better predictability and greater scalability compared with the traditional communication architectures.Application-specific NoCs(ASNoCs)have been demonstrated to be superior to regular NoCs in terms of power,area,and performance for SoCs that comprise heterogeneous cores with large variations in size.However,due to the ASNoC topology is designed to meet the bandwidth requirements and latency constraints between the cores of SoC for a certain application,it will bring the waste of network resources and increase the power consumption.Many researchers proposed run-time reconfigurable technique to adapt the changing communication conditions for reducing the power consumption of ASNoC and enhancing the flexibility.And,the topology generation for ASNoC is a NP-hard problem.Therefore,this dissertation concentrates on the topology generation methods for ASNoCs.In this dissertation,two dynamically reconfigurable topology generation methods are proposed for the applications with high bandwidth requirements and low bandwidth requirements,respectively.The main contributions are as follows:Study on the problem of allocating the routing paths for ASNoC.In this dissertation,an ILP and Lagrangian Relaxation based routing path allocation algorithms are proposed for routing the traffic flows while minimizing the power consumption under constraints,such as physical link capacity constraints,switch port constraints,and latency constraints.What is more,a modified shortest path algorithm based on the back-tracking method is proposed to find a deadlock-free least cost routing path for traffic flows.The results demonstrate the effectiveness of the proposed routing path allocation algorithm,which can ensure a low power consumption and improve the success rate.Study on the reconfigurable topology generation for ASNoC with RF-Interconnect.Taking advantages of the reconfigurability and high bandwidth of Radio Frequency Interconnect(RF-I),this dissertation brings RF-I technology into the ASNoC design and proposes a method to generate dynamically reconfigurable topologies for ASNoCs.Firstly,an integrated framework in a simulated annealing based searching is proposed to explore the proper clustering and floorplanning of cores,where the cores belonging to the same cluster will share the same switch for communications,and occupy a contiguous physical region to reduce the link power consumption.Secondly,we propose a method to allocate the RF-I logical channels one by one time interval.For each time interval,the link exhaustive method of integrating the allocation of routing paths is proposed to allocate the RF-I logical channels one by one.And,an iterative method is taken to optimize the allocation of RF-I logical channels and generate the dynamically reconfigurable ASNoC topologies for the given application while minimizing the power consumption and the reconfiguration costs of routing tables.Finally,a dynamical programming-based method is proposed to calculate the routing corners of transmission line,and a simulated annealing-based method is proposed to adjust the placement of the switches while minimizing the number of RF-I routing corners.Experimental results show that,using the RF-I,the power consumption of ASNoCs can be reduced by 20%-26%for the applications with high bandwidth requirements.Study on the reconfigurable topology generation for ASNoC on FPGA.Taking advantages of the reconfigurability of Field-Programmable Gate Array(FPGA),this dissertation proposes a method to generate dynamically reconfigurable topologies for ASNoCs where the computing units and communication architecture,are configured dynamically,simultaneously.Firstly,an integrated framework in a simulated annealing based searching is proposed to explore the proper schedule and floorplan of task modules,where a binary search-based heuristic method is proposed to solve the temporal partition of communications and evaluate the power consumption of NoC.Secondly,an ILP-based method is proposed to partition the communication requirements of the application into several time intervals while minimizing the communication requirements between time intrvals and balancing the communication requirements among all the time intervals.Finally,the routing path allocation problem is solved for each time interval to generate the corresponding ASNoC.And,an iterative method is taken to optimize the dynamically reconfigurable ASNoC topologies for the given application while minimizing the power consumption and the reconfiguration costs of routing tables.The results show that,the reconfigurable ASNoC can achieve 30.7%power consumption improvement with 2.1%reconfigurable time overhead when compared with static ASNoC.