Research Of Topology Generation Algorithm For Application Specific Network-on-Chip

With the increasing multi-applications of electronic products, the number ofintegrated heterogenous IP cores is increasing dramatically on a single chip. Thecommunication efficiency between these IP cores has become the key factor todetermine the system performance of multiprocessor system on chip (MPSoC). Theapplication specific Network-on-Chip (NoC) has emerged as a promising method toachieve high performance while induce low overhead for MPSoC. It can provide anoptimal network architecture according to the properties of specific applicationincluding the communication traffic and the size of IP cores, etc. Application specificNoC design is composed of Front-End design, Architectural Design and Back-Enddesign. In particular, Front-End deisgn determines the interconnection architecture,thereby becoming the basis of application specific NoC design.This thesis mainly focuses on the topology generation algorithm for Front-Enddeisgn of application specific NoC. To begin with, a system level archiecture designflow is proposed. According to this flow, new NoCs that can satisfy the applicationrequirements can be obtained. The flow consists of IP core clustering, floorplan andtopology generation as well as system performance evaluation methods. Fuzzyclustering is used to partition the IP cores to clusters so that the inner clustercommunication traffic is larger than that of inter clusters. In addition, different clusterscan be obtained on the basis of varied levels of intercept. With the cluster results, agenetic algorithm based model is established to implement the IP core floorplanning.Based on the physical link length gained from floorplan, this thesis proposes atopology generation algorithm that can generate scale free network automatically. Thistopology generation procedure starts with an initial netwok that has the small worldcharacter. Then, the residual IP cores will be added to the network dynamically, andhence an optimal network topology with the smallest power consumption can bedesigned. Moreover, the proposed topology generation algorithm is used for VOPDapplication. Eventually, an efficient OPNET based system development methodologythat can explore system level performance evaluation simulator is introduced in thisthesis. The methodology covers the simulator development flow and simulation resultsanalysis. The results demonstrate that the proposed topology generation algorithm cangenerate optimal network architecture that satisfies the requirements of sepcifc application. In addition, efficient network configuration can be obtained from thesystem level simulation as well.