Application-Specific Networks-on-Chip Design Methodologies: Traffic Modeling, Topology Construction And Automatic Generation

As the feature size shrinking to nanometer scale and chip areas expanding, globalwires delay increasing to several system clocks, traditional bus based and peer-to-peer based structures cannot meet the communication requirements of systems-on-chip(SoCs). Using data packet transmission scheme, Networks-on-chip (NoCs) provide ef-fective, reliable and ?exible infrastructures for system modules, and are becoming oneof the most potential solutions for SoC intra-communications. Application-specificnetworks-on-chip are necessary because chips have limited area, power and perfor-mance for on-chip networks, and are possible because on-chip systems have determin-istic communication requirements which can be utilized. In this thesis, we presentdesign methodologies for application-specific NoCs including on-chip traffic patternmodeling, network topology construction and source code automatic generation.We present an object-message modeling method for network-based SoCs, whichbuilds system prototypes by object-oriented methods, conducts object-to-core synthesisand function call-to-message mapping, and then accomplishes system partition andtraffic pattern abstraction. An H.263 prototype is developed to verify the method.We transform the problem of topology construction to module ?oorplan and traf-fic routing on discrete planes. The optimization goals include the transmission energy,the execution time and the area cost of NoCs. We define discrete plane properties anddemonstrate four instances. The point-splitting ?oorplan algorithm adapts the couplingbetween systems and networks, and can save 30% energy and 20% execution time com-pared with random ?oorplan results. The serial-parallel mixed traffic routing algorithmlinks modules by shortest paths and can save 10%– 30% discrete plane resources.We define a source-based routing and wormhole switching network protocolwhich suits irregular topologies and simple routers. We present a configurable routertemplate providing a huge design space for on-chip networks, and realize HDL sourcecode automatic generation. A series of routers generated by the program is synthesized and relations between the routers cost and the template parameters are determined.