Design Techniques For Nanoscale Low-power SAR A/D Converters

Successive approximation register analog-to-digital converters (SAR ADCs) arewidely used in medium-speed medium-resolution applications such as biomedicaldevices, wireless sensor nodes, and consumer electronic systems. To make life-time ofdevices which powered by battery or wireless energy, the low power SAR ADC designis becoming more critical. With the advancement of technology, SAR ADCs realizedbased on nanoscale CMOS process can also meet the requirement for high-speedapplications and achieve lower power.First, a low-speed low-power SAR ADC is designed in this thesis. By analyzingthe switching energy of several capacitor switching procedures, a novel energy-efficientcapacitor switching procedure is proposed. Furthermore, detailed analysis of offset andnoise of dynamic comparator is presented. Finally, dynamic logic is introduced toreduce the digital power consumption. The prototype was fabricated in SMIC0.18μmCMOS technology. At1.0V supply voltage and200KS/s, the ADC achieves SNDR of56.42dB and consumes1.4μW. The thesis also presents a high-speed asynchronousconfigurable SAR ADC for multi-accuracy and wide bandwidth applications. Thecapacitor switching procedure, high-speed comparator, SAR logic and asynchronouscontrol circuit have been designed in detail. The post-layout simulation results show, theADC achieves an SNDR of49.0dB and consumes1.56mW at8-bit and200MS/s mode;At10-bit and100MS/s, the ADC provides an SNDR of59.28dB and draws1.06mWfrom a1.0V supply.