A Study Of 8 Bit Low Voltage Low Power 10KSPS SAR ADC

Recently, with the advancement of large-scale integrated circuits, there has been a growing interest in the design of wireless sensor network for implantable, portable, and wearable applications. A few small size energy harvesting devices are used in power supply systems of low power wireless sensor network to reduce the battary replacing frequency and prolong the life of the node. The sensed signals are usually digitized by ADCs with moderate resolution(8~12 bits) and sampling rate(1~1000 k S/s) and power effeciency. Successive approximation register analog-to-digital converters(SAR ADCs) are suitable for application in wireless sensor network due to its simple architecture, small size, low power, easy integration, etc.Fistly, operational principle of SAR ADC is introduced in this thesis. Secondly, switching energy and switching linearity of capacitive DAC referring to the capacitor mismatch is analyzed in detail. Thirdly, a 0.3-V 8-bit 10 KSPS low-power SAR ADC is designed in this thesis. By analyzing the swithing energy of several conventional capacitor switching scheme, two novel energy-efficient capacitor switching architectures are proposed. One switching scheme is based on the spliting capacitor V CM-based switching procedure. In the sampling phase, bottom plates of the capacitors are connected to GND. After the sampling phase, bottom plates of the capacitors are switched to V CM, changing the input common mode voltage from V CM to V DD. By taking advantage of the dummy capacitor in the last conversion step, the total number and area of the capacitors have been reduces by half to gain the same resolution. The other proposed swithing procedure is based on the sub-DAC merging switching scheme. This novel switching architecture wastes no energy in the first two steps. Meanwhile, the area and energy consumption of the capacitor arrays are reduced by 75% and 98.4% respectively, comparing with the conventional switching scheme. Furthermore, a double-boosted and high linearity S/H switch is proposed. This double-boosted S/H switch is simple and the sampling switch in the conventional scheme is devided into two same switches to increase the linearity. The bodies of the switches can be switched into the source or the GND, further improve the linearity. Then, a novel dynamic comparator with bulk-driven technique has been introduced, especially the detailed description of a low leakage dynamic logical structure. Finally, several matters needing attention in designing layout are presented.The prototype of the SAR ADC based on the splitting capacitor V CM-based switching proced ure was fabricated in SMIC 0.18μm 1P6 M 1.8V CMOS process. The measurement results show that SAR ADC achieves 54.3 d B SFDR and 45.21 d B SNDR with Nyquist input at 10 k Hz,-0.3LSB/+0.12 LSB DNL and-0.38LSB/+0.38 LSB INL. The ENOB as a function of input frequency from 1 k Hz to 20 k Hz is over 7 bit of the low power SAR ADC. In addition, this SAR ADC can work normally with the supply voltage from 0.3V to 0.5V.