Research On 10-bit Low-power SAR-TDC Hybrid ADC

With the development of large-scale integrated circuits and the continuous reduction of process size,the Internet of Things technology has been vigorously developed,which in turn promotes the rapid development of many application scenarios such as wearable devices and smart homes.In these scenarios,electronic devices need to have high energy efficiency while maintaining normal functions to extend the use cycle as much as possible.However,the application of a large number of wireless sensors for collecting analog signals will cause excessive power consumption of the entire system.The Analog-to-Digital Converter(ADC),as a key module for connecting analog input signal and digital signal processing chip in wireless sensors,has always been the focus of researchers'attention.More digital circuits and good digital circuits compatibility make Successive Approximation Register(SAR)ADCs stand out among many ADC architectures and have become a research hotspot in recent years.The resolution in the time domain increases with the decrease of the supply voltage.Therefore,based on the Voltage-to-Time Converter(VTC)and the Time-to-Digital Converter(TDC)structure of ADCs also attract the attention of researchers.This article mainly studies the low-power technology of key circuits and implementation of SAR-TDC hybrid ADC.Aiming at many problems faced by the design of key modules in low-power ADCs under extremely low power supply,this article firstly introduces main points in each module design of low-power SAR ADCs and time domain data converter,and then a low-power hybrid SAR ADC is designed based on the SMIC 40nm 1P8M CMOS process.The main innovations of this article are listed below.Firstly,according to the characteristics of low-power SAR ADCs,a new capacitor DAC switching scheme is designed,which achieves 98%saving in switching energy and 86.91%reduction in capacitor area over the conventional scheme.Besides,comprehensive analysis of many factors such as common mode level variation,linearity,parasitic capacitance and V_cm reference level accuracy prove that the new switching scheme has a good performance.Secondly,in the design of the sampling switch,the linearity of the sampling signal at low supply voltage can be guaranteed by using the bootstrap technology,and the use of the substrate bias technology in the sampling process and the coupling signal elimination technology in the holding process make the sampling switch achieving 89.03d B SNDR at 0.4V supply voltage and 200KS/s sampling rate.Thirdly,the combination of asynchronous dynamic logic and comparator clock generation circuit achieve the latching of ADC output,the clock generation of comparator and capacitor bottom plate level switching,which improves the accuracy of the output and reduces the complexity of the external clock.Fourth,the hybrid SAR-TDC ADC combines the voltage domain and the time domain,which greatly reduces the difficulty of the voltage quantization of the traditional SAR ADC caused by the extremely low power supply.Based on the SMIC 40nm 1P8M CMOS process,the simulation results show that when the power supply voltage is 0.4V and the sampling rate is 200KS/s,the proposed SAR ADC achieves 58.74d B SFDR,56.48d B SNDR and ENOB of 9.09 bits with Nyquist input respectively.The overall power consumption is 143n W and the maximum DNL and INL are-0.62/+0.35LSB and-1.03/+1.02LSB.