Offset calibration techniques for high-speed CMOS flash analog-to-digital converters

This dissertation presents the research on the offset calibration techniques for high-speed CMOS flash ADCs. The main issue for the digitally controlled current trimming and capacitance trimming is that additional capacitive loading introduced into the high-speed analog signal path by calibration devices can degrade the high-speed performance for multi-GS/s flash ADCs. In reference voltage trimming, though there is no additional capacitive loading in the analog signal path, special implementations and extra devices are required in the resistor ladder.;The bulk voltage trimming and triode-load bias voltage trimming are proposed for CMOS flash ADCs. In bulk voltage trimming, the trim voltages are directly connected to the bulks of input pairs of the preamplifier. In triode-load bias voltage trimming, the trim voltages are directly connected to the bias voltages of the triode loads in the preamplifier. These two techniques do not introduce any additional capacitive loading in the analog signal path. Therefore the high-speed performance of a flash ADC is not impaired due to calibration.;A 4-bit flash ADC with bulking voltage trimming technique was fabricated in 90 nm CMOS. The prototype occupies 0.135-mm2 active area. The ADC consumes 86 mW at 5 GS/s with an input of 2.5 GHz. The measured peak DNL and INL are 0.43 LSB and 0.37 LSB respectively for a 4-MHz input at 5 GS/s. The ADC achieves 3.71 ENOB at 5 GS/s with 2.5-GHz ERBW and a 1.32-pJ/convstep FOM. When operating at 6GS/s, the ENOB is 3.75 for a 4-MHz input and 3.10 for a-2 GHz input.;Another 4-bit flash ADC with triode-load voltage trimming technique was designed in 65 nm CMOS. The active area is 0.0828mm2 . The ADC consumes 34.3 mW at 5 GS/s with an input of 2.5 GHz. The measured DNL and INL after calibration are -0.44~0.41 LSB and -0.39~0.44 LSB respectively for a 4-MHz input at 5 GS/s. The ADC achieves 3.93 ENOB at 5 GS/s with 2.5-GHz ERBW and a 0.45-pJ/convstep FOM.