Design And Implementation Of High Performance And Low Power SRAM

SRAM as the most important semiconductor memory is widely embedded intohigh performance mircroprocessors. With the upgrade of IC manufacturing technology,the ratio of memory power to chip power is bigger and bigger, and the design of highperformance and low power SRAMs becomes more and more important.Combining design flows of full-custom and semi-custom designed by standard cellbut implemented by hand floorplan and route, the paper has researched design,implementation, verification techniques about high performance and low power SRAMs,detailedly including:(1) High-speed SRAM design and implementation at65nm technology.Based on a13T1W/1R memory cell with an asynchronous reset port, the SRAMhas high read operation stability and low leakage current but large writing delay andlayout area. To compensate those defects, the paper proposes a low power bitlinestrategy of sharing bitlines for two bitlines writing structure. Read decoder and readoutcircuits sacrifice area and power to achieve faster readout speed, which helps the SRAMreduce the output delay by41.62%comparing with the same capacity SRAM generatedby Memory Compiler. For the implementation mode, peripheral circuits are designed bystandard cell but implemented by hand floorplan and route, which shortens the designperiod. By script languages, the paper develops an automatic verification flow ofcircuits and layouts with higher simulation accuracy.(2) High-performance SRAM design and implementation at40nm technology.Based on a10T1W/2R memory cell, the SRAM adopts high performance and lowpower design techniques such as two-level dynamic decoder, hierarchical readoutstructure of dynamic precharge, LSDL circuit, pulsing and gating clocks. The paperanalyzes and optimizes the dynamic pre-decoder reliability, the leakage current existingin dynamic decoder and precharge readout structure, and those guarantee that theSRAM can work normally at a low frequency (20MHz). As the experiment resultsshowing, comparing with the similar SRAM generated by Memory Compiler, the areaand delay and power of the SRAM designed by full-custom are reduced by7.67%and35.33%and39.66%respectively.The two memories designed in the paper meet the performance of SRAMsembedded in two DSP chips respectively, and lay a foundation for further studies onhigh performance and low power SRAMs about dual-port8T or cell with anasynchronous reset port.