The Research And Design Of Key Circuit For65nm High-performance SRAM

With the development of mobile Internet technology, the speed of the embedded process and system on chip is growing, thus promoting the cache acquirement for speed. As the central component of the cache, the SRAM has been the key to improve system’s speed.Based on the demand for high performance embedded CPU, in this paper we study the theoretical model of high speed SRAM, the optimization of structure, and the analysis of the critical circuit, This article analyz and improve the existing high speed SRAM design technique emphatically. The high performance SRAM is a SRAM which can work in a high speed, its speed is mainly reflected in time delay between the address input and data output, and the delay modules including the address buffer input、address decode、word-line enable、bitcell、bit-line output sense amplifier and output buffer etc.,According to the delay modules we just have outlined, this paper come up with some techniques and circuit structures which can optimize the speed of SRAM, as following:1. Introducing the distribution rc model for the decoding circuit interconnect, providing a more accuracy model for the decoder circuit optimization, taking into account the impact of the wire parasitism combining the process features and traditional delay model. To achieve the design and optimization for the high performance decoder circuit via the positive size of the transistors in SRAM decoder circuit according to the theoretical models of delay optimization.2. The important component of the high performance SRAM is bit cell, it usually determine the structure and stability of memory system. This paper proposed the asymmetric six T memory bit cell, which using the single read operation form and same proportion three MOS transistor size to increase the read drive ability with low threshold transistors. In addition, we use the hierarchical bit line structure to fit the cutdown process adhibition due to the increasing line parasitic influence. 3. Using the way of hierarchical bit line form can improve the operating speed of the large capacity SRAM,on the basic of traditional bit line classification,this paper deduced a more optimizing classification structure by analysising the speed of the bit line discharge which can accelerate the discharge speed of the bit line by decreasing the bit line capacitance to achieve sysytem speed improvement.And design and simulate the corresponding circuit under the SMIC65nm process so that we demonstrate the validity of the analysis.Through the above analysis and reaseach,we finally establish a optimization delay model and design technique for high performance SRAM decoder circuit combined with asymmetric six bit cell and optimizing classification bit-line technology.And also design a high performance4Kb SRAM base on SMIC65nm low leakage process.lt has been verified by the simulation when the voltage is1.2V,the access time is0.514ns and the frequency is1.5GHz.